Investigation of electrically active defects at the interface of high-k dielectrics and compound semiconductors

As silicon based devices in integrated circuits reach the fundamental limits of dimensional scaling there is growing research interest in the use of high electron mobility channel materials, such as indium gallium arsenide (InGaAs), in conjunction with high dielectric constant (high-k) gate oxides, for Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) based devices. The motivation for employing high mobility channel materials is to reduce power dissipation in integrated circuits while also providing improved performance. One of the primary challenges to date in the field of III-V semiconductors has been the observation of high levels of defect densities at the high-k/III-V interface, which prevents surface inversion of the semiconductor. The work presented in this PhD thesis details the characterization of MOS devices incorporating high-k dielectrics on III-V semiconductors. The analysis examines the effect of modifying the semiconductor bandgap in MOS structures incorporating InxGa1-xAs (x: 0, 0.15. 0.3, 0.53) layers, the optimization of device passivation procedures designed to reduce interface defect densities, and analysis of such electrically active interface defect states for the high-k/InGaAs system. Devices are characterized primarily through capacitance-voltage (CV) and conductance-voltage (GV) measurements of MOS structures both as a function of frequency and temperature. In particular, the density of electrically active interface states was reduced to the level which allowed the observation of true surface inversion behavior in the In0.53Ga0.47As MOS system. This was achieved by developing an optimized (NH4)2S passivation, minimized air exposure, and atomic layer deposition of an Al2O3 gate oxide. An extraction of activation energies allows discrimination of the mechanisms responsible for the inversion response. Finally a new approach is described to determine the minority carrier generation lifetime and the oxide capacitance in MOS structures. The method is demonstrated for an In0.53Ga0.47As system, but is generally applicable to any MOS structure exhibiting a minority carrier response in inversion.

Development of InAlN HEMTs for space application

This thesis investigates the emerging InAlN high electron mobility transistor (HEMT) technology with respect to its application in the space industry. The manufacturing processes and device performance of InAlN HEMTs were compared to AlGaN HEMTs, also produced as part of this work. RF gain up to 4 GHz was demonstrated in both InAlN and AlGaN HEMTs with gate lengths of 1 μm, with InAlN HEMTs generally showing higher channel currents (~150 c.f. 60 mA/mm) but also degraded leakage properties (~ 1 x 10-4 c.f. < 1 x 10-8 A/mm) with respect to AlGaN. An analysis of device reliability was undertaken using thermal stability, radiation hardness and off-state breakdown measurements. Both InAlN and AlGaN HEMTs showed excellent stability under space-like conditions, with electrical operation maintained after exposure to 9.2 Mrad of gamma radiation at a dose rate of 6.6 krad/hour over two months and after storage at 250°C for four weeks. Furthermore a link was established between the optimisation of device performance (RF gain, power handling capabilities and leakage properties) and reliability (radiation hardness, thermal stability and breakdown properties), particularly with respect to surface passivation. Following analysis of performance and reliability data, the InAlN HEMT device fabrication process was optimised by adjusting the metal Ohmic contact formation process (specifically metal stack thicknesses and anneal conditions) and surface passivation techniques (plasma power during dielectric layer deposition), based on an existing AlGaN HEMT process. This resulted in both a reduction of the contact resistivity to around 1 x 10-4 Ω.cm2 and the suppression of degrading trap-related effects, bringing the measured gate-lag close to zero. These discoveries fostered a greater understanding of the physical mechanisms involved in device operation and manufacture, which is elaborated upon in the final chapter.

MOVPE growth and characterization of Al(Ga)N and InAlN/AlGaN quantum wells for UV LED applications

The study of III-nitride materials (InN, GaN and AlN) gained huge research momentum after breakthroughs in the production light emitting diodes (LEDs) and laser diodes (LDs) over the past two decades. Last year, the Nobel Prize in Physics was awarded jointly to Isamu Akasaki, Hiroshi Amano and Shuji Nakamura for inventing a new energy efficient and environmental friendly light source: blue light-emitting diode (LED) from III-nitride semiconductors in the early 1990s. Nowadays, III-nitride materials not only play an increasingly important role in the lighting technology, but also become prospective candidates in other areas, for example, the high frequency (RF) high electron mobility transistor (HEMT) and photovoltaics. These devices require the growth of high quality III-nitride films, which can be prepared using metal organic vapour phase epitaxy (MOVPE). The main aim of my thesis is to study and develop the growth of III-nitride films, including AlN, u-AlGaN, Si-doped AlGaN, and InAlN, serving as sample wafers for fabrication of ultraviolet (UV) LEDs, in order to replace the conventional bulky, expensive and environmentally harmful mercury lamp as new UV light sources. For application to UV LEDs, reducing the threading dislocation density (TDD) in AlN epilayers on sapphire substrates is a key parameter for achieving high-efficiency AlGaNbased UV emitters. In Chapter 4, after careful and systematic optimisation， a working set of conditions, the screw and edge type dislocation density in the AlN were reduced to around 2.2×108 cm-2 and 1.3×109 cm-2 , respectively, using an optimized three-step process, as estimated by TEM. An atomically smooth surface with an RMS roughness of around 0.3 nm achieved over 5×5 µm 2 AFM scale. Furthermore, the motion of the steps in a one dimension model has been proposed to describe surface morphology evolution, especially the step bunching feature found under non-optimal conditions. In Chapter 5, control of alloy composition and the maintenance of compositional uniformity across a growing epilayer surface were demonstrated for the development of u-AlGaN epilayers. Optimized conditions (i.e. a high growth temperature of 1245 °C) produced uniform and smooth film with a low RMS roughness of around 2 nm achieved in 20×20 µm 2 AFM scan. The dopant that is most commonly used to obtain n-type conductivity in AlxGa1-xN is Si. However, the incorporation of Si has been found to increase the strain relaxation and promote unintentional incorporation of other impurities (O and C) during Si-doped AlGaN growth. In Chapter 6, reducing edge-type TDs is observed to be an effective appoach to improve the electric and optical properties of Si-doped AlGaN epilayers. In addition, the maximum electron concentration of 1.3×1019 cm-3 and 6.4×1018 cm-3 were achieved in Si-doped Al0.48Ga0.52N and Al0.6Ga0.4N epilayers as measured using Hall effect. Finally, in Chapter 7, studies on the growth of InAlN/AlGaN multiple quantum well (MQW) structures were performed, and exposing InAlN QW to a higher temperature during the ramp to the growth temperature of AlGaN barrier (around 1100 °C) will suffer a significant indium (In) desorption. To overcome this issue, quasi-two-tempeature (Q2T) technique was applied to protect InAlN QW. After optimization, an intense UV emission from MQWs has been observed in the UV spectral range from 320 to 350 nm measured by room temperature photoluminescence.

Atomic layer deposition of interface control layers for the fabrication of III/V MOS devices

The continued advancement of metal oxide semiconductor field effect transistor (MOSFET) technology has shifted the focus from Si/SiO2 transistors towards high-κ/III-V transistors for high performance, faster devices. This has been necessary due to the limitations associated with the scaling of the SiO2 thickness below ~1 nm and the associated increased leakage current due to direct electron tunnelling through the gate oxide. The use of these materials exhibiting lower effective charge carrier mass in conjunction with the use of a high-κ gate oxide allows for the continuation of device scaling and increases in the associated MOSFET device performance. The high-κ/III-V interface is a critical challenge to the integration of high-κ dielectrics on III-V channels. The interfacial chemistry of the high-κ/III-V system is more complex than Si, due to the nature of the multitude of potential native oxide chemistries at the surface with the resultant interfacial layer showing poor electrical insulating properties when high-κ dielectrics are deposited directly on these oxides. It is necessary to ensure that a good quality interface is formed in order to reduce leakage and interface state defect density to maximise channel mobility and reduce variability and power dissipation. In this work, the ALD growth of aluminium oxide (Al2O3) and hafnium oxide (HfO2) after various surface pre-treatments was carried out, with the aim of improving the high-κ/III-V interface by reducing the Dit – the density of interface defects caused by imperfections such as dangling bonds, dimers and other unsatisfied bonds at the interfaces of materials. A brief investigation was performed into the structural and electrical properties of Al2O3 films deposited on In0.53Ga0.47As at 200 and 300oC via a novel amidinate precursor. Samples were determined to experience a severe nucleation delay when deposited directly on native oxides, leading to diminished functionality as a gate insulator due to largely reduced growth per cycle. Aluminium oxide MOS capacitors were prepared by ALD and the electrical characteristics of GaAs, In0.53Ga0.47As and InP capacitors which had been exposed to pre-pulse treatments from triethyl gallium and trimethyl indium were examined, to determine if self-cleaning reactions similar to those of trimethyl aluminium occur for other alkyl precursors. An improved C-V characteristic was observed for GaAs devices indicating an improved interface possibly indicating an improvement of the surface upon pre-pulsing with TEG, conversely degraded electrical characteristics observed for In0.53Ga0.47As and InP MOS devices after pre-treatment with triethyl gallium and trimethyl indium respectively. The electrical characteristics of Al2O3/In0.53Ga0.47As MOS capacitors after in-situ H2/Ar plasma treatment or in-situ ammonium sulphide passivation were investigated and estimates of interface Dit calculated. The use of plasma reduced the amount of interface defects as evidenced in the improved C-V characteristics. Samples treated with ammonium sulphide in the ALD chamber were found to display no significant improvement of the high-κ/III-V interface. HfO2 MOS capacitors were fabricated using two different precursors comparing the industry standard hafnium chloride process with deposition from amide precursors incorporating a ~1nm interface control layer of aluminium oxide and the structural and electrical properties investigated. Capacitors furnished from the chloride process exhibited lower hysteresis and improved C-V characteristics as compared to that of hafnium dioxide grown from an amide precursor, an indication that no etching of the film takes place using the chloride precursor in conjunction with a 1nm interlayer. Optimisation of the amide process was carried out and scaled samples electrically characterised in order to determine if reduced bilayer structures display improved electrical characteristics. Samples were determined to exhibit good electrical characteristics with a low midgap Dit indicative of an unpinned Fermi level

First principles calculation of electron-phonon and alloy scattering in strained SiGe

First-principles electronic structure methods are used to predict the mobility of n-type carrier scattering in strained SiGe. We consider the effects of strain on the electron-phonon deformation potentials and the alloy scattering parameters. We calculate the electron-phonon matrix elements and fit them up to second order in strain. We find, as expected, that the main effect of strain on mobility comes from the breaking of the degeneracy of the six Δ and L valleys, and the choice of transport direction. The non-linear effects on the electron-phonon coupling of the Δ valley due to shear strain are found to reduce the mobility of Si-like SiGe by 50% per % strain. We find increases in mobility between 2 and 11 times that of unstrained SiGe for certain fixed Ge compositions, which should enhance the thermoelectric figure of merit in the same order, and could be important for piezoresistive applications.

AuxAg1-x alloy seeds: A way to control growth, morphology and defect formation in Ge nanowires

Germanium (Ge) nanowires are of current research interest for high speed nanoelectronic devices due to the lower band gap and high carrier mobility compatible with high K-dielectrics and larger excitonic Bohr radius ensuing a more pronounced quantum confinement effect [1-6]. A general way for the growth of Ge nanowires is to use liquid or a solid growth promoters in a bottom-up approach which allow control of the aspect ratio, diameter, and structure of 1D crystals via external parameters, such as precursor feedstock, temperature, operating pressure, precursor flow rate etc [3, 7-11]. The Solid-phase seeding is preferred for more control processing of the nanomaterials and potential suppression of the unintentional incorporation of high dopant concentrations in semiconductor nanowires and unrequired compositional tailing of the seed-nanowire interface [2, 5, 9, 12]. There are therefore distinct features of the solid phase seeding mechanism that potentially offer opportunities for the controlled processing of nanomaterials with new physical properties. A superior control over the growth kinetics of nanowires could be achieved by controlling the inherent growth constraints instead of external parameters which always account for instrumental inaccuracy. The high dopant concentrations in semiconductor nanowires can result from unintentional incorporation of atoms from the metal seed material, as described for the Al catalyzed VLS growth of Si nanowires [13] which can in turn be depressed by solid-phase seeding. In addition, the creation of very sharp interfaces between group IV semiconductor segments has been achieved by solid seeds [14], whereas the traditionally used liquid Au particles often leads to compositional tailing of the interface [15] . Korgel et al. also described the superior size retention of metal seeds in a SFSS nanowire growth process, when compared to a SFLS process using Au colloids [12]. Here in this work we have used silver and alloy seed particle with different compositions to manipulate the growth of nanowires in sub-eutectic regime. The solid seeding approach also gives an opportunity to influence the crystallinity of the nanowires independent of the substrate. Taking advantage of the readily formation of stacking faults in metal nanoparticles, lamellar twins in nanowires could be formed.

A study of silicon and germanium junctionless transistors

Technology boosters, such as strain, HKMG and FinFET, have been introduced into semiconductor industry to extend Moore’s law beyond 130 nm technology nodes. New device structures and channel materials are highly demanded to keep performance enhancement when the device scales beyond 22 nm. In this work, the properties and feasibility of the proposed Junctionless transistor (JNT) have been evaluated for both Silicon and Germanium channels. The performance of Silicon JNTs with 22 nm gate length have been characterized at elevated temperature and stressed conditions. Furthermore, steep Subthreshold Slopes (SS) in JNT and IM devices are compared. It is observed that the floating body in JNT is relatively dynamic comparing with that in IM devices and proper design of the device structure may further reduce the VD for a sub- 60 mV/dec subthreshold slope. Diode configuration of the JNT has also been evaluated, which demonstrates the first diode without junctions. In order to extend JNT structure into the high mobility material Germanium (Ge), a full process has been develop for Ge JNT. Germanium-on-Insulator (GeOI) wafers were fabricated using Smart-Cut with low temperature direct wafer bonding method. Regarding the lithography and pattern transfer, a top-down process of sub-50-nm width Ge nanowires is developed in this chapter and Ge nanowires with 35 nm width and 50 nm depth are obtained. The oxidation behaviour of Ge by RTO has been investigated and high-k passivation scheme using thermally grown GeO2 has been developed. With all developed modules, JNT with Ge channels have been fabricated by the CMOScompatible top-down process. The transistors exhibit the lowest subthreshold slope to date for Ge JNT. The devices with a gate length of 3 μm exhibit a SS of 216 mV/dec with an ION/IOFF current ratio of 1.2×103 at VD = -1 V and DIBL of 87 mV/V.

Resist-substrate interface tailoring for generating high density arrays of Ge and Bi2Se3 nanowires by electron beam lithography

The authors report a chemical process to remove the native oxide on Ge and Bi2Se3 crystals, thus facilitating high-resolution electron beam lithography (EBL) on their surfaces using a hydrogen silsesquioxane (HSQ) resist. HSQ offers the highest resolution of all the commercially available EBL resists. However, aqueous HSQ developers such as NaOH and tetramethylammonium hydroxide have thus far prevented the fabrication of high-resolution structures via the direct application of HSQ to Ge and Bi2Se3, due to the solubility of components of their respective native oxides in these strong aqueous bases. Here we provide a route to the generation of ordered, high-resolution, high-density Ge and Bi2Se3 nanostructures with potential applications in microelectronics, thermoelectric, and photonics devices.                         

Electron beam lithography assisted high-resolution pattern generation

This thesis details the top-down fabrication of nanostructures on Si and Ge substrates by electron beam lithography (EBL). Various polymeric resist materials were used to create nanopatterns by EBL and Chapter 1 discusses the development characteristics of these resists. Chapter 3 describes the processing parameters, resolution and topographical and structural changes of a new EBL resist known as ‘SML’. A comparison between SML and the standard resists PMMA and ZEP520A was undertaken to determine the suitability of SML as an EBL resist. It was established that SML is capable of high-resolution patterning and showed good pattern transfer capabilities. Germanium is a desirable material for use in microelectronic applications due to a number of superior qualities over silicon. EBL patterning of Ge with high-resolution hydrogen silsesquioxane (HSQ) resist is however difficult due to the presence of native surface oxides. Thus, to combat this problem a new technique for passivating Ge surfaces prior to EBL processes is detailed in Chapter 4. The surface passivation was carried out using simple acids like citric acid and acetic acid. The acids were gentle on the surface and enabled the formation of high-resolution arrays of Ge nanowires using HSQ resist. Chapter 5 details the directed self-assembly (DSA) of block copolymers (BCPs) on EBL patterned Si and, for the very first time, Ge surfaces. DSA of BCPs on template substrates is a promising technology for high volume and cost effective nanofabrication. The BCP employed for this study was poly (styrene-b-ethylene oxide) and the substrates were pre-defined by HSQ templates produced by EBL. The DSA technique resulted into pattern rectification (ordering in BCP) and in pattern multiplication within smaller areas.