Average-case analysis of power consumption in embedded systems

Power efficiency is one of the most important constraints in the design of embedded systems since such systems are generally driven by batteries with limited energy budget or restricted power supply. In every embedded system, there are one or more processor cores to run the software and interact with the other hardware components of the system. The power consumption of the processor core(s) has an important impact on the total power dissipated in the system. Hence, the processor power optimization is crucial in satisfying the power consumption constraints, and developing low-power embedded systems. A key aspect of research in processor power optimization and management is “power estimation”. Having a fast and accurate method for processor power estimation at design time helps the designer to explore a large space of design possibilities, to make the optimal choices for developing a power efficient processor. Likewise, understanding the processor power dissipation behaviour of a specific software/application is the key for choosing appropriate algorithms in order to write power efficient software. Simulation-based methods for measuring the processor power achieve very high accuracy, but are available only late in the design process, and are often quite slow. Therefore, the need has arisen for faster, higher-level power prediction methods that allow the system designer to explore many alternatives for developing powerefficient hardware and software. The aim of this thesis is to present fast and high-level power models for the prediction of processor power consumption. Power predictability in this work is achieved in two ways: first, using a design method to develop power predictable circuits; second, analysing the power of the functions in the code which repeat during execution, then building the power model based on average number of repetitions. In the first case, a design method called Asynchronous Charge Sharing Logic (ACSL) is used to implement the Arithmetic Logic Unit (ALU) for the 8051 microcontroller. The ACSL circuits are power predictable due to the independency of their power consumption to the input data. Based on this property, a fast prediction method is presented to estimate the power of ALU by analysing the software program, and extracting the number of ALU-related instructions. This method achieves less than 1% error in power estimation and more than 100 times speedup in comparison to conventional simulation-based methods. In the second case, an average-case processor energy model is developed for the Insertion sort algorithm based on the number of comparisons that take place in the execution of the algorithm. The average number of comparisons is calculated using a high level methodology called MOdular Quantitative Analysis (MOQA). The parameters of the energy model are measured for the LEON3 processor core, but the model is general and can be used for any processor. The model has been validated through the power measurement experiments, and offers high accuracy and orders of magnitude speedup over the simulation-based method.

Politics, Power, PISA: a genealogy of mathematics education policy at second level in Ireland at the beginning of the 21st century

This thesis traces a genealogy of the discourse of mathematics education reform in Ireland at the beginning of the twenty first century at a time when the hegemonic political discourse is that of neoliberalism. It draws on the work of Michel Foucault to identify the network of power relations involved in the development of a single case of curriculum reform – in this case Project Maths. It identifies the construction of an apparatus within the fields of politics, economics and education, the elements of which include institutions like the OECD and the Government, the bureaucracy, expert groups and special interest groups, the media, the school, the State, state assessment and international assessment. Five major themes in educational reform emerge from the analysis: the arrival of neoliberal governance in Ireland; the triumph of human capital theory as the hegemonic educational philosophy here; the dominant role of OECD/PISA and its values in the mathematics education discourse in Ireland; the fetishisation of western scientific knowledge and knowledge as commodity; and the formation of a new kind of subjectivity, namely the subjectivity of the young person as a form of human-capital-to-be. In particular, it provides a critical analysis of the influence of OECD/PISA on the development of mathematics education policy here – especially on Project Maths curriculum, assessment and pedagogy. It unpacks the arguments in favour of curriculum change and lays bare their ideological foundations. This discourse contextualises educational change as occurring within a rapidly changing economic environment where the concept of the State’s economic aspirations and developments in science, technology and communications are reshaping both the focus of business and the demands being put on education. Within this discourse, education is to be repurposed and its consequences measured against the paradigm of the Knowledge Economy – usually characterised as the inevitable or necessary future of a carefully defined present.

All-optical modulation converter for on-off keying to duobinary and alternate-mark inversion at 42.6 Gbps

Advanced modulation formats have become increasingly important as telecoms engineers strive for improved tolerance to both linear and nonlinear fibre-based transmission impairments. Two important modulation schemes are Duobinary (DB) and Alternate-mark inversion (AMI) [1] where transmission enhancement results from auxiliary phase modulation. As advanced modulation formats displace Return-to-zero On-Off Keying (RZ-OOK), inter-modulation converters will become increasingly important. If the modulation conversion can be performed at high bitrates with a small number of operations per bit, then all-optical techniques may offer lower energy consumption compared to optical-electronic-optical approaches. In this paper we experimentally demonstrate an all-optical system incorporating a pair of hybrid-integrated semiconductor optical amplifier (SOA)-based Mach-Zehnder interferometer (MZI) gates which translate RZ-OOK to RZ-DB or RZ-AMI at 42.6 Gbps. This scheme includes a wavelength conversion to arbitrary output wavelength and has potential for high-level photonic integration, scalability to higher bitrates, and should exhibit regenerative properties [2].

DC/DC converter 3D assembly for autonomous sensor nodes

This paper reports on the design and the manufacturing of an integrated DCDC converter, which respects the specificity of sensor node network: compactness, high efficiency in acquisition and transmission modes, and compatibility with miniature Lithium batteries. A novel integrated circuit (ASIC) has been designed and manufactured to provide regulated Voltage to the sensor node from miniaturized, thin film Lithium batteries. Then, a 3D integration technique has been used to integrate this ASIC in a 3 layers stack with high efficiency passives components, mixing the wafer level technologies from two different research institutions. Electrical results have demonstrated the feasibility of this integrated system and experiments have shown significant improvements in the case of oscillations in regulated voltage. However, stability of this output voltage toward the input voltage has still to be improved.

Systematic delay-driven power optimisation and power-driven delay optimisation of combinational circuits

With the proliferation of mobile wireless communication and embedded systems, the energy efficiency becomes a major design constraint. The dissipated energy is often referred as the product of power dissipation and the input-output delay. Most of electronic design automation techniques focus on optimising only one of these parameters either power or delay. Industry standard design flows integrate systematic methods of optimising either area or timing while for power consumption optimisation one often employs heuristics which are characteristic to a specific design. In this work we answer three questions in our quest to provide a systematic approach to joint power and delay Optimisation. The first question of our research is: How to build a design flow which incorporates academic and industry standard design flows for power optimisation? To address this question, we use a reference design flow provided by Synopsys and integrate in this flow academic tools and methodologies. The proposed design flow is used as a platform for analysing some novel algorithms and methodologies for optimisation in the context of digital circuits. The second question we answer is: Is possible to apply a systematic approach for power optimisation in the context of combinational digital circuits? The starting point is a selection of a suitable data structure which can easily incorporate information about delay, power, area and which then allows optimisation algorithms to be applied. In particular we address the implications of a systematic power optimisation methodologies and the potential degradation of other (often conflicting) parameters such as area or the delay of implementation. Finally, the third question which this thesis attempts to answer is: Is there a systematic approach for multi-objective optimisation of delay and power? A delay-driven power and power-driven delay optimisation is proposed in order to have balanced delay and power values. This implies that each power optimisation step is not only constrained by the decrease in power but also the increase in delay. Similarly, each delay optimisation step is not only governed with the decrease in delay but also the increase in power. The goal is to obtain multi-objective optimisation of digital circuits where the two conflicting objectives are power and delay. The logic synthesis and optimisation methodology is based on AND-Inverter Graphs (AIGs) which represent the functionality of the circuit. The switching activities and arrival times of circuit nodes are annotated onto an AND-Inverter Graph under the zero and a non-zero-delay model. We introduce then several reordering rules which are applied on the AIG nodes to minimise switching power or longest path delay of the circuit at the pre-technology mapping level. The academic Electronic Design Automation (EDA) tool ABC is used for the manipulation of AND-Inverter Graphs. We have implemented various combinatorial optimisation algorithms often used in Electronic Design Automation such as Simulated Annealing and Uniform Cost Search Algorithm. Simulated Annealing (SMA) is a probabilistic meta heuristic for the global optimization problem of locating a good approximation to the global optimum of a given function in a large search space. We used SMA to probabilistically decide between moving from one optimised solution to another such that the dynamic power is optimised under given delay constraints and the delay is optimised under given power constraints. A good approximation to the global optimum solution of energy constraint is obtained. Uniform Cost Search (UCS) is a tree search algorithm used for traversing or searching a weighted tree, tree structure, or graph. We have used Uniform Cost Search Algorithm to search within the AIG network, a specific AIG node order for the reordering rules application. After the reordering rules application, the AIG network is mapped to an AIG netlist using specific library cells. Our approach combines network re-structuring, AIG nodes reordering, dynamic power and longest path delay estimation and optimisation and finally technology mapping to an AIG netlist. A set of MCNC Benchmark circuits and large combinational circuits up to 100,000 gates have been used to validate our methodology. Comparisons for power and delay optimisation are made with the best synthesis scripts used in ABC. Reduction of 23% in power and 15% in delay with minimal overhead is achieved, compared to the best known ABC results. Also, our approach is also implemented on a number of processors with combinational and sequential components and significant savings are achieved.

Grid integration of wave energy & generic modelling of ocean devices for power system studies

The work presented in this thesis covers four major topics of research related to the grid integration of wave energy. More specifically, the grid impact of a wave farm on the power quality of its local network is investigated. Two estimation methods were developed regarding the flicker level Pst generated by a wave farm in relation to its rated power as well as in relation to the impedance angle ψk of the node in the grid to which it is connected. The electrical design of a typical wave farm design is also studied in terms of minimum rating for three types of costly pieces of equipment, namely the VAr compensator, the submarine cables and the overhead line. The power losses dissipated within the farm's electrical network are also evaluated. The feasibility of transforming a test site into a commercial site of greater rated power is investigated from the perspective of power quality and of cables and overhead line thermal loading. Finally, the generic modelling of ocean devices, referring here to both wave and tidal current devices, is investigated.

Integrated magnetic components for high-power high-current dc-dc converters

This thesis is focused on the design and development of an integrated magnetic (IM) structure for use in high-power high-current power converters employed in renewable energy applications. These applications require low-cost, high efficiency and high-power density magnetic components and the use of IM structures can help achieve this goal. A novel CCTT-core split-winding integrated magnetic (CCTT IM) is presented in this thesis. This IM is optimized for use in high-power dc-dc converters. The CCTT IM design is an evolution of the traditional EE-core integrated magnetic (EE IM). The CCTT IM structure uses a split-winding configuration allowing for the reduction of external leakage inductance, which is a problem for many traditional IM designs, such as the EE IM. Magnetic poles are incorporated to help shape and contain the leakage flux within the core window. These magnetic poles have the added benefit of minimizing the winding power loss due to the airgap fringing flux as they shape the fringing flux away from the split-windings. A CCTT IM reluctance model is developed which uses fringing equations to accurately predict the most probable regions of fringing flux around the pole and winding sections of the device. This helps in the development of a more accurate model as it predicts the dc and ac inductance of the component. A CCTT IM design algorithm is developed which relies heavily on the reluctance model of the CCTT IM. The design algorithm is implemented using the mathematical software tool Mathematica. This algorithm is modular in structure and allows for the quick and easy design and prototyping of the CCTT IM. The algorithm allows for the investigation of the CCTT IM boxed volume with the variation of input current ripple, for different power ranges, magnetic materials and frequencies. A high-power 72 kW CCTT IM prototype is designed and developed for use in an automotive fuelcell-based drivetrain. The CCTT IM design algorithm is initially used to design the component while 3D and 2D finite element analysis (FEA) software is used to optimize the design. Low-cost and low-power loss ferrite 3C92 is used for its construction, and when combined with a low number of turns results in a very efficient design. A paper analysis is undertaken which compares the performance of the high-power CCTT IM design with that of two discrete inductors used in a two-phase (2L) interleaved converter. The 2L option consists of two discrete inductors constructed from high dc-bias material. Both topologies are designed for the same worst-case phase current ripple conditions and this ensures a like-for-like comparison. The comparison indicates that the total magnetic component boxed volume of both converters is similar while the CCTT IM has significantly lower power loss. Experimental results for the 72 kW, (155 V dc, 465 A dc input, 420 V dc output) prototype validate the CCTT IM concept where the component is shown to be 99.7 % efficient. The high-power experimental testing was conducted at General Motors advanced technology center in Torrence, Los Angeles. Calorific testing was used to determine the power loss in the CCTT IM component. Experimental 3.8 kW results and a 3.8 kW prototype compare and contrast the ferrite CCTT IM and high dc-bias 2L concepts over the typical operating range of a fuelcell under like-for-like conditions. The CCTT IM is shown to perform better than the 2L option over the entire power range. An 8 kW ferrite CCTT IM prototype is developed for use in photovoltaic (PV) applications. The CCTT IM is used in a boost pre-regulator as part of the PV power stage. The CCTT IM is compared with an industry standard 2L converter consisting of two discrete ferrite toroidal inductors. The magnetic components are compared for the same worst-case phase current ripple and the experimental testing is conducted over the operation of a PV panel. The prototype CCTT IM allows for a 50 % reduction in total boxed volume and mass in comparison to the baseline 2L option, while showing increased efficiency.

Integrated spot size converters for InP based photonic systems

The ever increasing demand for broadband communications requires sophisticated devices. Photonic integrated circuits (PICs) are an approach that fulfills those requirements. PICs enable the integration of different optical modules on a single chip. Low loss fiber coupling and simplified packaging are key issues in keeping the price of PICs at a low level. Integrated spot size converters (SSC) offer an opportunity to accomplish this. Design, fabrication and characterization of SSCs based on an asymmetric twin waveguide (ATG) at a wavelength of 1.55 μm are the main elements of this dissertation. It is theoretically and experimentally shown that a passive ATG facilitates a polarization filter mechanism. A reproducible InP process guideline is developed that achieves vertical waveguides with smooth sidewalls. Birefringence and resonant coupling are used in an ATG to enable a polarization filtering and splitting mechanism. For the first time such a filter is experimentally shown. At a wavelength of 1610 nm a power extinction ratio of (1.6 ± 0.2) dB was measured for the TE- polarization in a single approximately 372 μm long TM- pass polarizer. A TE-pass polarizer with a similar length was demonstrated with a TM/TE-power extinction ratio of (0.7 ± 0.2) dB at 1610 nm. The refractive indices of two different InGaAsP compositions, required for a SSC, are measured by the reflection spectroscopy technique. A SSC layout for dielectric-free fabricated compact photodetectors is adjusted to those index values. The development and the results of the final fabrication procedure for the ATG concept are outlined. The etch rate, sidewall roughness and selectivity of a Cl2/CH4/H2 based inductively coupled plasma (ICP) etch are investigated by a design of experiment approach. The passivation effect of CH4 is illustrated for the first time. Conditions are determined for etching smooth and vertical sidewalls up to a depth of 5 μm.

Energy harvesting system design and optimization for wireless sensor networks

Wireless sensor networks (WSN) are becoming widely adopted for many applications including complicated tasks like building energy management. However, one major concern for WSN technologies is the short lifetime and high maintenance cost due to the limited battery energy. One of the solutions is to scavenge ambient energy, which is then rectified to power the WSN. The objective of this thesis was to investigate the feasibility of an ultra-low energy consumption power management system suitable for harvesting sub-mW photovoltaic and thermoelectric energy to power WSNs. To achieve this goal, energy harvesting system architectures have been analyzed. Detailed analysis of energy storage units (ESU) have led to an innovative ESU solution for the target applications. Battery-less, long-lifetime ESU and its associated power management circuitry, including fast-charge circuit, self-start circuit, output voltage regulation circuit and hybrid ESU, using a combination of super-capacitor and thin film battery, were developed to achieve continuous operation of energy harvester. Low start-up voltage DC/DC converters have been developed for 1mW level thermoelectric energy harvesting. The novel method of altering thermoelectric generator (TEG) configuration in order to match impedance has been verified in this work. Novel maximum power point tracking (MPPT) circuits, exploring the fractional open circuit voltage method, were particularly developed to suit the sub-1mW photovoltaic energy harvesting applications. The MPPT energy model has been developed and verified against both SPICE simulation and implemented prototypes. Both indoor light and thermoelectric energy harvesting methods proposed in this thesis have been implemented into prototype devices. The improved indoor light energy harvester prototype demonstrates 81% MPPT conversion efficiency with 0.5mW input power. This important improvement makes light energy harvesting from small energy sources (i.e. credit card size solar panel in 500lux indoor lighting conditions) a feasible approach. The 50mm × 54mm thermoelectric energy harvester prototype generates 0.95mW when placed on a 60oC heat source with 28% conversion efficiency. Both prototypes can be used to continuously power WSN for building energy management applications in typical office building environment. In addition to the hardware development, a comprehensive system energy model has been developed. This system energy model not only can be used to predict the available and consumed energy based on real-world ambient conditions, but also can be employed to optimize the system design and configuration. This energy model has been verified by indoor photovoltaic energy harvesting system prototypes in long-term deployed experiments.

Resonant power conversion topologies for inductive charging of electrical vehicle batteries

This thesis is concerned with inductive charging of electric vehicle batteries. Rectified power form the 50/60 Hz utility feeds a dc-ac converter which delivers high-frequency ac power to the electric vehicle inductive coupling inlet. The inlet configuration has been defined by the Society of Automotive Engineers in Recommended Practice J-1773. This thesis studies converter topologies related to the series resonant converter. When coupled to the vehicle inlet, the frequency-controlled series-resonant converter results in a capacitively-filtered series-parallel LCLC (SP-LCLC) resonant converter topology with zero voltage switching and many other desirable features. A novel time-domain transformation analysis, termed Modal Analysis, is developed, using a state variable transformation, to analyze and characterize this multi-resonant fourth-orderconverter. Next, Fundamental Mode Approximation (FMA) Analysis, based on a voltage-source model of the load, and its novel extension, Rectifier-Compensated FMA (RCFMA) Analysis, are developed and applied to the SP-LCLC converter. The RCFMA Analysis is a simpler and more intuitive analysis than the Modal Analysis, and provides a relatively accurate closed-form solution for the converter behavior. Phase control of the SP-LCLC converter is investigated as a control option. FMA and RCFMA Analyses are used for detailed characterization. The analyses identify areas of operation, which are also validated experimentally, where it is advantageous to phase control the converter. A novel hybrid control scheme is proposed which integrates frequency and phase control and achieves reduced operating frequency range and improved partial-load efficiency. The phase-controlled SP-LCLC converter can also be configured with a parallel load and is an excellent option for the application. The resulting topology implements soft-switching over the entire load range and has high full-load and partial-load efficiencies. RCFMA Analysis is used to analyze and characterize the new converter topology, and good correlation is shown with experimental results. Finally, a novel single-stage power-factor-corrected ac-dc converter is introduced, which uses the current-source characteristic of the SP-LCLC topology to provide power factor correction over a wide output power range from zero to full load. This converter exhibits all the advantageous characteristics of its dc-dc counterpart, with a reduced parts count and cost. Simulation and experimental results verify the operation of the new converter.

High-current inductors for high-power automotive DC-DC converters

This thesis is focused on the investigation of magnetic materials for high-power dcdc converters in hybrid and fuel cell vehicles and the development of an optimized high-power inductor for a multi-phase converter. The thesis introduces the power system architectures for hybrid and fuel cell vehicles. The requirements for power electronic converters are established and the dc-dc converter topologies of interest are introduced. A compact and efficient inductor is critical to reduce the overall cost, weight and volume of the dc-dc converter and optimize vehicle driving range and traction power. Firstly, materials suitable for a gapped CC-core inductor are analyzed and investigated. A novel inductor-design algorithm is developed and automated in order to compare and contrast the various magnetic materials over a range of frequencies and ripple ratios. The algorithm is developed for foil-wound inductors with gapped CC-cores in the low (10 kHz) to medium (30 kHz) frequency range and investigates the materials in a natural-convection-cooled environment. The practical effects of frequency, ripple, air-gap fringing, and thermal configuration are investigated next for the iron-based amorphous metal and 6.5 % silicon steel materials. A 2.5 kW converter is built to verify the optimum material selection and thermal configuration over the frequency range and ripple ratios of interest. Inductor size can increase in both of these laminated materials due to increased airgap fringing losses. Distributing the airgap is demonstrated to reduce the inductor losses and size but has practical limitations for iron-based amorphous metal cores. The effects of the manufacturing process are shown to degrade the iron-based amorphous metal multi-cut core loss. The experimental results also suggest that gap loss is not a significant consideration in these experiments. The predicted losses by the equation developed by Reuben Lee and cited by Colonel McLyman are significantly higher than the experimental results suggest. Iron-based amorphous metal has better preformance than 6.5 % silicon steel when a single cut core and natural-convection-cooling are used. Conduction cooling, rather than natural convection, can result in the highest power density inductor. The cooling for these laminated materials is very dependent on the direction of the lamination and the component mounting. Experimental results are produced showing the effects of lamination direction on the cooling path. A significant temperature reduction is demonstrated for conduction cooling versus natural-convection cooling. Iron-based amorphous metal and 6.5% silicon steel are competitive materials when conduction cooled. A novel inductor design algorithm is developed for foil-wound inductors with gapped CC-cores for conduction cooling of core and copper. Again, conduction cooling, rather than natural convection, is shown to reduce the size and weight of the inductor. The weight of the 6.5 % silicon steel inductor is reduced by around a factor of ten compared to natural-convection cooling due to the high thermal conductivity of the material. The conduction cooling algorithm is used to develop high-power custom inductors for use in a high power multi-phase boost converter. Finally, a high power digitally-controlled multi-phase boost converter system is designed and constructed to test the high-power inductors. The performance of the inductors is compared to the predictions used in the design process and very good correlation is achieved. The thesis results have been documented at IEEE APEC, PESC and IAS conferences in 2007 and at the IEEE EPE conference in 2008.

Can population-level variation in early childhood development be measured in a manner that supports service planning and intervention?

Background: The Early Development Instrument (EDI) is a population-level measure of five developmental domains at school-entry age. The overall aim of this thesis was to explore the potential of the EDI as an indicator of early development in Ireland. Methods: A cross-sectional study was conducted in 47 primary schools in 2011 using the EDI and a linked parental questionnaire. EDI (teacher completed) scores were calculated for 1,344 children in their first year of full-time education. Those scoring in the lowest 10% of the sample population in one or more domains were deemed to be 'developmentally vulnerable'. Scores were correlated with contextual data from the parental questionnaire and with indicators of area and school-level deprivation. Rasch analysis was used to determine the validity of the EDI. Results: Over one quarter (27.5%) of all children in the study were developmentally vulnerable. Individual characteristics associated with increased risk of vulnerability were being male; under 5 years old; and having English as a second language. Adjusted for these demographics, low birth weight, poor parent/child interaction and mother’s lower level of education showed the most significant odds ratios for developmental vulnerability. Vulnerability did not follow the area-level deprivation gradient as measured by a composite index of material deprivation. Children considered by the teacher to be in need of assessment also had lower scores, which were not significantly different from those of children with a clinical diagnosis of special needs. all domains showed at least reasonable fit to the Rasch model supporting the validity of the instrument. However, there was a need for further refinement of the instrument in the Irish context. Conclusion: This thesis provides a unique snapshot of early development in Ireland. The EDI and linked parental questionnaires are promising indicators of the extent, distribution and determinants of developmental vulnerability.