Magnetic multilayer fabrication technology with selective activation of SU-8 films

Developing magnetic multilayers are essential for reducing the core eddy current losses in the integrated power magnetic components (inductors/transformers). PVD based processes are typically used to achieve the multilayers with thin dielectric spacers. However, those processes are costly, and can be difficult to integrate. It is evident that cost effective alternative is needed. In recent years, electrochemical processes have been investigated to address these issues. One such method would be to successive metallization of insulating photoresists acting as spacer layer (such as SU-8) with soft magnetic films (such as Ni-Fe-Co alloys). This paper describes an experimental procedure to fabricate magnetic multilayers with a thin variant of SU-8 2 (< 1.5 µm) as inter-layers for integrated micro-inductors/transformers for power conversion applications.

Atomic layer deposition of interface control layers for the fabrication of III/V MOS devices

The continued advancement of metal oxide semiconductor field effect transistor (MOSFET) technology has shifted the focus from Si/SiO2 transistors towards high-κ/III-V transistors for high performance, faster devices. This has been necessary due to the limitations associated with the scaling of the SiO2 thickness below ~1 nm and the associated increased leakage current due to direct electron tunnelling through the gate oxide. The use of these materials exhibiting lower effective charge carrier mass in conjunction with the use of a high-κ gate oxide allows for the continuation of device scaling and increases in the associated MOSFET device performance. The high-κ/III-V interface is a critical challenge to the integration of high-κ dielectrics on III-V channels. The interfacial chemistry of the high-κ/III-V system is more complex than Si, due to the nature of the multitude of potential native oxide chemistries at the surface with the resultant interfacial layer showing poor electrical insulating properties when high-κ dielectrics are deposited directly on these oxides. It is necessary to ensure that a good quality interface is formed in order to reduce leakage and interface state defect density to maximise channel mobility and reduce variability and power dissipation. In this work, the ALD growth of aluminium oxide (Al2O3) and hafnium oxide (HfO2) after various surface pre-treatments was carried out, with the aim of improving the high-κ/III-V interface by reducing the Dit – the density of interface defects caused by imperfections such as dangling bonds, dimers and other unsatisfied bonds at the interfaces of materials. A brief investigation was performed into the structural and electrical properties of Al2O3 films deposited on In0.53Ga0.47As at 200 and 300oC via a novel amidinate precursor. Samples were determined to experience a severe nucleation delay when deposited directly on native oxides, leading to diminished functionality as a gate insulator due to largely reduced growth per cycle. Aluminium oxide MOS capacitors were prepared by ALD and the electrical characteristics of GaAs, In0.53Ga0.47As and InP capacitors which had been exposed to pre-pulse treatments from triethyl gallium and trimethyl indium were examined, to determine if self-cleaning reactions similar to those of trimethyl aluminium occur for other alkyl precursors. An improved C-V characteristic was observed for GaAs devices indicating an improved interface possibly indicating an improvement of the surface upon pre-pulsing with TEG, conversely degraded electrical characteristics observed for In0.53Ga0.47As and InP MOS devices after pre-treatment with triethyl gallium and trimethyl indium respectively. The electrical characteristics of Al2O3/In0.53Ga0.47As MOS capacitors after in-situ H2/Ar plasma treatment or in-situ ammonium sulphide passivation were investigated and estimates of interface Dit calculated. The use of plasma reduced the amount of interface defects as evidenced in the improved C-V characteristics. Samples treated with ammonium sulphide in the ALD chamber were found to display no significant improvement of the high-κ/III-V interface. HfO2 MOS capacitors were fabricated using two different precursors comparing the industry standard hafnium chloride process with deposition from amide precursors incorporating a ~1nm interface control layer of aluminium oxide and the structural and electrical properties investigated. Capacitors furnished from the chloride process exhibited lower hysteresis and improved C-V characteristics as compared to that of hafnium dioxide grown from an amide precursor, an indication that no etching of the film takes place using the chloride precursor in conjunction with a 1nm interlayer. Optimisation of the amide process was carried out and scaled samples electrically characterised in order to determine if reduced bilayer structures display improved electrical characteristics. Samples were determined to exhibit good electrical characteristics with a low midgap Dit indicative of an unpinned Fermi level

Fabrication of sub-10 nm lamellar structures by solvent vapour annealing of block copolymers

Fabrication of nanoscale patterns through the bottom-up approach of self-assembly of phase-separated block copolymers (BCP) holds promise for nanoelectronics applications. For lithographic applications, it is useful to vary the morphology of BCPs by monitoring various parameters to make “from lab to fab” a reality. Here I report on the solvent annealing studies of lamellae forming polystyrene-blockpoly( 4-vinylpyridine) (PS-b-P4VP). The high Flory-Huggins parameter (χ = 0.34) of PS-b-P4VP makes it an ideal BCP system for self-assembly and template fabrication in comparison to other BCPs. Different molecular weights of symmetric PS-b-P4VP BCPs forming lamellae patterns were used to produce nanostructured thin films by spin-coating from mixture of toluene and tetrahydrofuran(THF). In particular, the morphology change from micellar structures to well-defined microphase separated arrangements is observed. Solvent annealing provides a better alternative to thermal treatment which often requires long annealing periods. The choice of solvent (single and dual solvent exposure) and the solvent annealing conditions have significant effects on the morphology of films and it was found that a block neutral solvent was required to realize vertically aligned PS and P4VP lamellae. Here, we have followed the formation of microdomain structures with time development at different temperatures by atomic force microscopy (AFM). The highly mobilized chains phase separate quickly due to high Flory-Huggins (χ) parameter. Ultra-small feature size (~10 nm pitch size) nanopatterns were fabricated by using low molecular weight PSb- P4VP (PS and P4VP blocks of 3.3 and 3.1 kg mol-1 respectively). However, due to the low etch contrast between the blocks, pattern transfer of the BCP mask is very challenging. To overcome the etch contrast problem, a novel and simple in-situ hard mask technology is used to fabricate the high aspect ratio silicon nanowires. The lamellar structures formed after self-assembly of phase separated PS-b-P4VP BCPs were used to fabricate iron oxide nanowires which acted as hard mask material to facilitate the pattern transfer into silicon and forming silicon nanostructures. The semiconductor and optical industries have shown significant interest in two dimensional (2D) molybdenum disulphide (MoS2) as a potential device material due to its low band gap and high mobility. However, current methods for its synthesis are not ‘fab’ friendly and require harsh environments and processes. Here, I also report a novel method to prepare MoS2 layered structures via self-assembly of a PS-b-P4VP block copolymer system. The formation of the layered MoS2 was confirmed by XPS, Raman spectroscopy and high resolution transmission electron microscopy.

Computational study of the growth of copper thin films by atomic layer deposition

Copper is the main interconnect material in microelectronic devices, and a 2 nm-thick continuous Cu film seed layer needs to be deposited to produce microelectronic devices with the smallest features and more functionality. Atomic layer deposition (ALD) is the most suitable method to deposit such thin films. However, the reaction mechanism and the surface chemistry of copper ALD remain unclear, which is deterring the development of better precursors and design of new ALD processes. In this thesis, we study the surface chemistries during ALD of copper by means of density functional theory (DFT). To understand the effect of temperature and pressure on the composition of copper with substrates, we used ab initio atomistic thermodynamics to obtain phase diagram of the Cu(111)/SiO2(0001) interface. We found that the interfacial oxide Cu2O phases prefer high oxygen pressure and low temperature while the silicide phases are stable at low oxygen pressure and high temperature for Cu/SiO2 interface, which is in good agreement with experimental observations. Understanding the precursor adsorption on surfaces is important for understanding the surface chemistry and reaction mechanism of the Cu ALD process. Focusing on two common Cu ALD precursors, Cu(dmap)2 and Cu(acac)2, we studied the precursor adsorption on Cu surfaces by means of van der Waals (vdW) inclusive DFT methods. We found that the adsorption energies and adsorption geometries are dependent on the adsorption sites and on the method used to include vdW in the DFT calculation. Both precursor molecules are partially decomposed and the Cu cations are partially reduced in their chemisorbed structure. It is found that clean cleavage of the ligand−metal bond is one of the requirements for selecting precursors for ALD of metals. 2 Bonding between surface and an atom in the ligand which is not coordinated with the Cu may result in impurities in the thin film. To have insight into the reaction mechanism of a full ALD cycle of Cu ALD, we proposed reaction pathways based on activation energies and reaction energies for a range of surface reactions between Cu(dmap)2 and Et2Zn. The butane formation and desorption steps are found to be extremely exothermic, explaining the ALD reaction scheme of original experimental work. Endothermic ligand diffusion and re-ordering steps may result in residual dmap ligands blocking surface sites at the end of the Et2Zn pulse, and in residual Zn being reduced and incorporated as an impurity. This may lead to very slow growth rate, as was the case in the experimental work. By investigating the reduction of CuO to metallic Cu, we elucidated the role of the reducing agent in indirect ALD of Cu. We found that CuO bulk is protected from reduction during vacuum annealing by the CuO surface and that H2 is required in order to reduce that surface, which shows that the strength of reducing agent is important to obtain fully reduced metal thin films during indirect ALD processes. Overall, in this thesis, we studied the surface chemistries and reaction mechanisms of Cu ALD processes and the nucleation of Cu to form a thin film.