Fabrication of sub-10 nm lamellar structures by solvent vapour annealing of block copolymers

Fabrication of nanoscale patterns through the bottom-up approach of self-assembly of phase-separated block copolymers (BCP) holds promise for nanoelectronics applications. For lithographic applications, it is useful to vary the morphology of BCPs by monitoring various parameters to make “from lab to fab” a reality. Here I report on the solvent annealing studies of lamellae forming polystyrene-blockpoly( 4-vinylpyridine) (PS-b-P4VP). The high Flory-Huggins parameter (χ = 0.34) of PS-b-P4VP makes it an ideal BCP system for self-assembly and template fabrication in comparison to other BCPs. Different molecular weights of symmetric PS-b-P4VP BCPs forming lamellae patterns were used to produce nanostructured thin films by spin-coating from mixture of toluene and tetrahydrofuran(THF). In particular, the morphology change from micellar structures to well-defined microphase separated arrangements is observed. Solvent annealing provides a better alternative to thermal treatment which often requires long annealing periods. The choice of solvent (single and dual solvent exposure) and the solvent annealing conditions have significant effects on the morphology of films and it was found that a block neutral solvent was required to realize vertically aligned PS and P4VP lamellae. Here, we have followed the formation of microdomain structures with time development at different temperatures by atomic force microscopy (AFM). The highly mobilized chains phase separate quickly due to high Flory-Huggins (χ) parameter. Ultra-small feature size (~10 nm pitch size) nanopatterns were fabricated by using low molecular weight PSb- P4VP (PS and P4VP blocks of 3.3 and 3.1 kg mol-1 respectively). However, due to the low etch contrast between the blocks, pattern transfer of the BCP mask is very challenging. To overcome the etch contrast problem, a novel and simple in-situ hard mask technology is used to fabricate the high aspect ratio silicon nanowires. The lamellar structures formed after self-assembly of phase separated PS-b-P4VP BCPs were used to fabricate iron oxide nanowires which acted as hard mask material to facilitate the pattern transfer into silicon and forming silicon nanostructures. The semiconductor and optical industries have shown significant interest in two dimensional (2D) molybdenum disulphide (MoS2) as a potential device material due to its low band gap and high mobility. However, current methods for its synthesis are not ‘fab’ friendly and require harsh environments and processes. Here, I also report a novel method to prepare MoS2 layered structures via self-assembly of a PS-b-P4VP block copolymer system. The formation of the layered MoS2 was confirmed by XPS, Raman spectroscopy and high resolution transmission electron microscopy.

Hardware design of cryptographic accelerators

With the rapid growth of the Internet and digital communications, the volume of sensitive electronic transactions being transferred and stored over and on insecure media has increased dramatically in recent years. The growing demand for cryptographic systems to secure this data, across a multitude of platforms, ranging from large servers to small mobile devices and smart cards, has necessitated research into low cost, flexible and secure solutions. As constraints on architectures such as area, speed and power become key factors in choosing a cryptosystem, methods for speeding up the development and evaluation process are necessary. This thesis investigates flexible hardware architectures for the main components of a cryptographic system. Dedicated hardware accelerators can provide significant performance improvements when compared to implementations on general purpose processors. Each of the designs proposed are analysed in terms of speed, area, power, energy and efficiency. Field Programmable Gate Arrays (FPGAs) are chosen as the development platform due to their fast development time and reconfigurable nature. Firstly, a reconfigurable architecture for performing elliptic curve point scalar multiplication on an FPGA is presented. Elliptic curve cryptography is one such method to secure data, offering similar security levels to traditional systems, such as RSA, but with smaller key sizes, translating into lower memory and bandwidth requirements. The architecture is implemented using different underlying algorithms and coordinates for dedicated Double-and-Add algorithms, twisted Edwards algorithms and SPA secure algorithms, and its power consumption and energy on an FPGA measured. Hardware implementation results for these new algorithms are compared against their software counterparts and the best choices for minimum area-time and area-energy circuits are then identified and examined for larger key and field sizes. Secondly, implementation methods for another component of a cryptographic system, namely hash functions, developed in the recently concluded SHA-3 hash competition are presented. Various designs from the three rounds of the NIST run competition are implemented on FPGA along with an interface to allow fair comparison of the different hash functions when operating in a standardised and constrained environment. Different methods of implementation for the designs and their subsequent performance is examined in terms of throughput, area and energy costs using various constraint metrics. Comparing many different implementation methods and algorithms is nontrivial. Another aim of this thesis is the development of generic interfaces used both to reduce implementation and test time and also to enable fair baseline comparisons of different algorithms when operating in a standardised and constrained environment. Finally, a hardware-software co-design cryptographic architecture is presented. This architecture is capable of supporting multiple types of cryptographic algorithms and is described through an application for performing public key cryptography, namely the Elliptic Curve Digital Signature Algorithm (ECDSA). This architecture makes use of the elliptic curve architecture and the hash functions described previously. These components, along with a random number generator, provide hardware acceleration for a Microblaze based cryptographic system. The trade-off in terms of performance for flexibility is discussed using dedicated software, and hardware-software co-design implementations of the elliptic curve point scalar multiplication block. Results are then presented in terms of the overall cryptographic system.

Formation of sub-7 nm feature size PS-b-P4VP block copolymer structures by solvent vapour process

The nanometer range structure produced by thin films of diblock copolymers makes them a great of interest as templates for the microelectronics industry. We investigated the effect of annealing solvents and/or mixture of the solvents in case of symmetric Poly (styrene-block-4vinylpyridine) (PS-b-P4VP) diblock copolymer to get the desired line patterns. In this paper, we used different molecular weights PS-b-P4VP to demonstrate the scalability of such high χ BCP system which requires precise fine-tuning of interfacial energies achieved by surface treatment and that improves the wetting property, ordering, and minimizes defect densities. Bare Silicon Substrates were also modified with polystyrene brush and ethylene glycol self-assembled monolayer in a simple quick reproducible way. Also, a novel and simple in situ hard mask technique was used to generate sub-7nm Iron oxide nanowires with a high aspect ratio on Silicon substrate, which can be used to develop silicon nanowires post pattern transfer.