DC/DC converter 3D assembly for autonomous sensor nodes

This paper reports on the design and the manufacturing of an integrated DCDC converter, which respects the specificity of sensor node network: compactness, high efficiency in acquisition and transmission modes, and compatibility with miniature Lithium batteries. A novel integrated circuit (ASIC) has been designed and manufactured to provide regulated Voltage to the sensor node from miniaturized, thin film Lithium batteries. Then, a 3D integration technique has been used to integrate this ASIC in a 3 layers stack with high efficiency passives components, mixing the wafer level technologies from two different research institutions. Electrical results have demonstrated the feasibility of this integrated system and experiments have shown significant improvements in the case of oscillations in regulated voltage. However, stability of this output voltage toward the input voltage has still to be improved.

A study of silicon and germanium junctionless transistors

Technology boosters, such as strain, HKMG and FinFET, have been introduced into semiconductor industry to extend Moore’s law beyond 130 nm technology nodes. New device structures and channel materials are highly demanded to keep performance enhancement when the device scales beyond 22 nm. In this work, the properties and feasibility of the proposed Junctionless transistor (JNT) have been evaluated for both Silicon and Germanium channels. The performance of Silicon JNTs with 22 nm gate length have been characterized at elevated temperature and stressed conditions. Furthermore, steep Subthreshold Slopes (SS) in JNT and IM devices are compared. It is observed that the floating body in JNT is relatively dynamic comparing with that in IM devices and proper design of the device structure may further reduce the VD for a sub- 60 mV/dec subthreshold slope. Diode configuration of the JNT has also been evaluated, which demonstrates the first diode without junctions. In order to extend JNT structure into the high mobility material Germanium (Ge), a full process has been develop for Ge JNT. Germanium-on-Insulator (GeOI) wafers were fabricated using Smart-Cut with low temperature direct wafer bonding method. Regarding the lithography and pattern transfer, a top-down process of sub-50-nm width Ge nanowires is developed in this chapter and Ge nanowires with 35 nm width and 50 nm depth are obtained. The oxidation behaviour of Ge by RTO has been investigated and high-k passivation scheme using thermally grown GeO2 has been developed. With all developed modules, JNT with Ge channels have been fabricated by the CMOScompatible top-down process. The transistors exhibit the lowest subthreshold slope to date for Ge JNT. The devices with a gate length of 3 μm exhibit a SS of 216 mV/dec with an ION/IOFF current ratio of 1.2×103 at VD = -1 V and DIBL of 87 mV/V.

Hybrid integration and packaging of grating-coupled silicon photonics

This thesis covers both the packaging of silicon photonic devices with fiber inputs and outputs as well as the integration of laser light sources with these same devices. The principal challenge in both of these pursuits is coupling light into the submicrometer waveguides that are the hallmark of silicon-on-insulator (SOI) systems. Previous work on grating couplers is leveraged to design new approaches to bridge the gap between the highly-integrated domain of silicon, the Interconnected world of fiber and the active region of III-V materials. First, a novel process for the planar packaging of grating couplers with fibers is explored in detail. This technology allows the creation of easy-to-use test platforms for laser integration and also stands on its own merits as an enabling technology for next-generation silicon photonics systems. The alignment tolerances of this process are shown to be well-suited to a passive alignment process and for wafer-scale assembly. Furthermore, this technology has already been used to package demonstrators for research partners and is included in the offerings of the ePIXfab silicon photonics foundry and as a design kit for PhoeniX Software’s MaskEngineer product. After this, a process for hybridly integrating a discrete edge-emitting laser with a silicon photonic circuit using near-vertical coupling is developed and characterized. The details of the various steps of the design process are given, including mechanical, thermal, optical and electrical steps. The interrelation of these design domains is also discussed. The construction process for a demonstrator is outlined, and measurements are presented of a series of single-wavelength Fabry-Pérot lasers along with a two-section laser tunable in the telecommunications C-band. The suitability and potential of this technology for mass manufacture is demonstrated, with further opportunities for improvement detailed and discussed in the conclusion.

Development of germanium/silicon integration for near infrared detection

Silicon (Si) is the base material for electronic technologies and is emerging as a very attractive platform for photonic integrated circuits (PICs). PICs allow optical systems to be made more compact with higher performance than discrete optical components. Applications for PICs are in the area of fibre-optic communication, biomedical devices, photovoltaics and imaging. Germanium (Ge), due to its suitable bandgap for telecommunications and its compatibility with Si technology is preferred over III-V compounds as an integrated on-chip detector at near infrared wavelengths. There are two main approaches for Ge/Si integration: through epitaxial growth and through direct wafer bonding. The lattice mismatch of ~4.2% between Ge and Si is the main problem of the former technique which leads to a high density of dislocations while the bond strength and conductivity of the interface are the main challenges of the latter. Both result in trap states which are expected to play a critical role. Understanding the physics of the interface is a key contribution of this thesis. This thesis investigates Ge/Si diodes using these two methods. The effects of interface traps on the static and dynamic performance of Ge/Si avalanche photodetectors have been modelled for the first time. The thesis outlines the original process development and characterization of mesa diodes which were fabricated by transferring a ~700 nm thick layer of p-type Ge onto n-type Si using direct wafer bonding and layer exfoliation. The effects of low temperature annealing on the device performance and on the conductivity of the interface have been investigated. It is shown that the diode ideality factor and the series resistance of the device are reduced after annealing. The carrier transport mechanism is shown to be dominated by generation–recombination before annealing and by direct tunnelling in forward bias and band-to-band tunnelling in reverse bias after annealing. The thesis presents a novel technique to realise photodetectors where one of the substrates is thinned by chemical mechanical polishing (CMP) after bonding the Si-Ge wafers. Based on this technique, Ge/Si detectors with remarkably high responsivities, in excess of 3.5 A/W at 1.55 μm at −2 V, under surface normal illumination have been measured. By performing electrical and optical measurements at various temperatures, the carrier transport through the hetero-interface is analysed by monitoring the Ge band bending from which a detailed band structure of the Ge/Si interface is proposed for the first time. The above unity responsivity of the detectors was explained by light induced potential barrier lowering at the interface. To our knowledge this is the first report of light-gated responsivity for vertically illuminated Ge/Si photodiodes. The wafer bonding approach followed by layer exfoliation or by CMP is a low temperature wafer scale process. In principle, the technique could be extended to other materials such as Ge on GaAs, or Ge on SOI. The unique results reported here are compatible with surface normal illumination and are capable of being integrated with CMOS electronics and readout units in the form of 2D arrays of detectors. One potential future application is a low-cost Si process-compatible near infrared camera.

Development of CMOS-compatible electrostatic supercapacitors

This work focuses on development of electrostatic supercapacitors (ESCs) using process routes compatible with complementary metal–oxide–semiconductor (CMOS) fabrication. Wafer-scale anodised aluminium oxide (AAO) processing techniques have been developed to produce high-surface area templates. Statistically optimised atomic layer deposition (ALD) processes have been developed to conformally coat the templates and generate metalinsulator-metal capacitor structures. Detailed electrical characterisation and analysis for a range of devices, revealed ESC’s with high capacitance densities of ~12 μF cm-2 and equivalent energy densities of 0.28 Wh/kg . Finally the suitability of ESC’s toward next generation energy storage applications is discussed.

Synthesis and characterization of oxide materials

Nanostructured materials are central to the evolution of future electronics and biomedical applications amongst other applications. This thesis is focused on developing novel methods to prepare a number of nanostructured metal oxide particles and films by a number of different routes. Part of the aim was to see how techniques used in nanoparticle science could be applied to thin film methods to develop functional surfaces. Wet-chemical methods were employed to synthesize and modify the metal oxide nanostructures (CeO2 and SiO2) and their structural properties were characterized through advanced X-ray diffraction, electron microscopy, photoelectron spectroscopy and other techniques. Whilst particulates have uses in many applications, their attachment to surfaces is of importance and this is frequently challenging. We examined the use of block copolymer methods to form very well defined metal oxide particulate-like structures on the surface of a number of substrates. Chapter 2 describes a robust method to synthesize various sized silica nanoparticles. As-synthesized silica nanoparticles were further functionalized with IR-820 and FITC dyes. The ability to create size controlled nanoparticles with associated (optical) functionality may have significant importance in bio-medical imaging. Thesis further describes how non-organic modified fluorescent particles might be prepared using inorganic oxides. A study of the concentrations and distributions of europium dopants within the CeO2 nanoparticles was undertaken and investigated by different microscopic and spectroscopic techniques. The luminescent properties were enhanced by doping and detailed explanations are reported. Additionally, the morphological and structural evolution and optical properties were correlated as a function of concentrations of europium doping as well as with further annealing. Further work using positron annihilation spectroscopy allowed the study of vacancy type defects formed due to europium doping in CeO2 crystallites and this was supported by complimentary UV-Vis spectra and XRD work. During the last few years the interest in mesoporous silica materials has increased due to their typical characteristics such as potential ultra-low dielectric constant materials, large surface area and pore volume, well-ordered and uniform pores with adjustable pores between 2 and 50 nm. A simple, generic and cost-effective route was used to demonstrate the synthesis of 2D mesoporous silica thin films over wafer scale dimensions in chapter 5. Lithographic resist and in situ hard mask block copolymer followed by ICP dry etching were used to fabricate mesoporous silica nanostructures. The width of mesoporous silica channels can be varied by using a variety of commercially available lithographic resists whereas depth of the mesoporous silica channels can be varied by altering the etch time. The crystal structure, morphology, pore arrangement, pore diameters, thickness of films and channels were determined by XRD, SEM, ellipsometry and the results reported. This project also extended work towards the study of the antimicrobial study of nanopatterned silver nanodot arrays formed using the block copolymer approach defined above. Silver nanodot arrays were successfully tested for antimicrobial activity over S. aureus and P. aeruginosa biofilms and results shows silver nanodots has good antimicrobial activity for both S. aureus and P. aeruginosa biofilms. Thus, these silver nanodot arrays shows a potential to be used as a substitute for the resolution of infection complications in many areas.

Less strain, more gain_nano_patterning III-N thin films

Controlling the growth mechanism for nano-structures is one of the most critical topics in material science. In the past 10 years there has been intensive research worldwide in IIIN based nanowires for its many unique photonic and electrical properties at this scale. There are several advantages to nanostructuring III-N materials, including increased light extraction, increased device efficiency, reduction of efficiency droop, and reduction in crystallographic defect density. High defect densities that normally plague III-N materials and reduce the device efficiency are not an issue for nano-structured devices such as LEDs, due to the effective strain relaxation. Additionally regions of the light spectrum such as green and yellow, once found difficult to achieve in bulk planar LEDs, can be produced by manipulating the confinement and crystal facet growth directions of the active regions. A cheap and easily repeatable self-assembly nano-patterning technique at wafer scale was designed during this thesis for top down production of III-N nanowires. Through annealing under ammonia and N2 gas flow, the first reported dislocation defect bending was observed in III-N nanorods by in-situ transmission electron microscopy heating. By growing on these etched top down nanorods as a template, ultra-dense nanowires with apex tipped semi-polar tops were produced. The uniform spacing of 5nm between each wire is the highest reported space-filling factor at 98%. Finally by using these ultra-dense nanorods bridging the green gap of the light spectrum was possible, producing the first reported red, yellow, green light emission from a single nano-tip.

Site controlled red-yellow-green light emitting InGaN quantum discs on nano-tipped GaN rods

We report a method of growing site controlled InGaN multiple quantum discs (QDs) at uniform wafer scale on coalescence free ultra-high density (>80%) nanorod templates by metal organic chemical vapour deposition (MOCVD). The dislocation and coalescence free nature of the GaN space filling nanorod arrays eliminates the well-known emission problems seen in InGaN based visible light sources that these types of crystallographic defects cause. Correlative scanning transmission electron microscopy (STEM), energy-dispersive X-ray (EDX) mapping and cathodoluminescence (CL) hyperspectral imaging illustrates the controlled site selection of the red, yellow and green (RYG) emission at these nano tips. This article reveals that the nanorod tips' broad emission in the RYG visible range is in fact achieved by manipulating the InGaN QD's confinement dimensions, rather than significantly increasing the In%. This article details the easily controlled method of manipulating the QDs dimensions producing high crystal quality InGaN without complicated growth conditions needed for strain relaxation and alloy compositional changes seen for bulk planar GaN templates.

A novel CE microchip with micro pillars column & double-L injection design for Capacitance Coupled Contactless Conductivity detection technology

This novel capillary electrophoresis microchip, or also known as μTAS (micro total analysis system) was designed to separate complex aqueous based compounds, similar to commercial CE & microchip (capillary electrophoresis) systems, but more compact. This system can be potentially used for mobile/portable chemical analysis equipment. Un-doped silicon wafer & ultra-thin borofloat glass (Pyrex) wafers have been used to fabricate the device. Double-L injection feature, micro pillars column, bypass separation channel & hybrid- referenced C4D electrodes were designed to achieve a high SNR (signal to noise ratio), easy- separation, for a durable and reusable μTAS for CE use.

Photonic packaging: transforming silicon photonic integrated circuits into photonic devices

Dedicated multi-project wafer (MPW) runs for photonic integrated circuits (PICs) from Si foundries mean that researchers and small-to-medium enterprises (SMEs) can now afford to design and fabricate Si photonic chips. While these bare Si-PICs are adequate for testing new device and circuit designs on a probe-station, they cannot be developed into prototype devices, or tested outside of the laboratory, without first packaging them into a durable module. Photonic packaging of PICs is significantly more challenging, and currently orders of magnitude more expensive, than electronic packaging, because it calls for robust micron-level alignment of optical components, precise real-time temperature control, and often a high degree of vertical and horizontal electrical integration. Photonic packaging is perhaps the most significant bottleneck in the development of commercially relevant integrated photonic devices. This article describes how the key optical, electrical, and thermal requirements of Si-PIC packaging can be met, and what further progress is needed before industrial scale-up can be achieved.