4 resultados para Reflection and design

em CORA - Cork Open Research Archive - University College Cork - Ireland


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This paper investigates the effects of antenna detuning on wireless devices caused by the presence of the human body,particularly the wrist. To facilitate repeatable and consistent antenna impedance measurements, an accurate and low cost human phantom arm, that simulates human tissue at 433MHz frequencies, has been developed and characterized. An accurate and low cost hardware prototype system has been developed to measure antenna return loss at a frequency of 433MHz and the design, fabrication and measured results are presented. This system provides a flexible means of evaluating closed-loop reconfigurable antenna tuning circuits for use in wireless mote applications.

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In the last decade, we have witnessed the emergence of large, warehouse-scale data centres which have enabled new internet-based software applications such as cloud computing, search engines, social media, e-government etc. Such data centres consist of large collections of servers interconnected using short-reach (reach up to a few hundred meters) optical interconnect. Today, transceivers for these applications achieve up to 100Gb/s by multiplexing 10x 10Gb/s or 4x 25Gb/s channels. In the near future however, data centre operators have expressed a need for optical links which can support 400Gb/s up to 1Tb/s. The crucial challenge is to achieve this in the same footprint (same transceiver module) and with similar power consumption as today’s technology. Straightforward scaling of the currently used space or wavelength division multiplexing may be difficult to achieve: indeed a 1Tb/s transceiver would require integration of 40 VCSELs (vertical cavity surface emitting laser diode, widely used for short‐reach optical interconnect), 40 photodiodes and the electronics operating at 25Gb/s in the same module as today’s 100Gb/s transceiver. Pushing the bit rate on such links beyond today’s commercially available 100Gb/s/fibre will require new generations of VCSELs and their driver and receiver electronics. This work looks into a number of state‐of-the-art technologies and investigates their performance restraints and recommends different set of designs, specifically targeting multilevel modulation formats. Several methods to extend the bandwidth using deep submicron (65nm and 28nm) CMOS technology are explored in this work, while also maintaining a focus upon reducing power consumption and chip area. The techniques used were pre-emphasis in rising and falling edges of the signal and bandwidth extensions by inductive peaking and different local feedback techniques. These techniques have been applied to a transmitter and receiver developed for advanced modulation formats such as PAM-4 (4 level pulse amplitude modulation). Such modulation format can increase the throughput per individual channel, which helps to overcome the challenges mentioned above to realize 400Gb/s to 1Tb/s transceivers.

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This research in progress paper addresses the IS issue in relation to conducting relevant research while keeping academic rigor. In particular, it contributes to the ongoing academic conversation around the investigation on how to incor-porate action in design science research. In this document the philosophical underpinnings of the recently proposed methodology called Action Design Re-search [1] are derived, outlined and integrated into Burrel and Morgan’s Par-adigmatic Framework (1979)[6]. The results so far show how Action Design Research can be considered as a particular case of Design Science Research (rather than a methodology closely related to Action Research) although they can assume two different epistemological positions. From these philosophical perspectives, future works will involve the inclusion of actual research projects using the three different methodologies. The final goal is to outline and structure the divergences and similarities of Action Design Research with Design Science Research and Canonical Action Research.

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In this paper, a wireless sensor network mote hardware design and implementation are introduced for building deployment application. The core of the mote design is based on the 8 bit AVR microcontroller, Atmega1281 and 2.4 GHz wireless communication chip, CC2420. The module PCB fabrication is using the stackable technology providing powerful configuration capability. Three main layers of size 25 mm2 are structured to form the mote; these are RF, sensor and power layers. The sensors were selected carefully to meet both the building monitoring and design requirements. Beside the sensing capability, actuation and interfacing to external meters/sensors are provided to perform different management control and data recording tasks. Experiments show that the developed mote works effectively in giving stable data acquisition and owns good communication and power performance.