Small angle scattering characterisation of micellar systems and templated architectures

The work described in this thesis reports the structural changes induced on micelles under a variety of conditions. The micelles of a liquid crystal film and dilute solutions of micelles were subjected to high pressure CO2 and selected hydrocarbon environments. Using small angle neutron scattering (SANS) techniques the spacing between liquid crystal micelles was measured in-situ. The liquid crystals studied were templated from different surfactants with varying structural characteristics. Micelles of a dilute surfactant solution were also subjected to elevated pressures of varying gas atmospheres. Detailed modelling of the in-situ SANS experiments revealed information of the size and shape of the micelles at a number of different pressures. Also reported in this thesis is the characterisation of mesoporous materials in the confined channels of larger porous materials. Periodic mesoporous organosilicas (PMOs) were synthesised within the channels of anodic alumina membranes (AAM) under different conditions, including drying rates and precursor concentrations. In-situ small angle x-ray scattering (SAXS) and transmission electron microscopy (TEM) was used to determine the pore morphology of the PMO within the AAM channels. PMO materials were also used as templates in the deposition of gold nanoparticles and subsequently used in the synthesis of germanium nanostructures. Polymer thin films were also employed as templates for the directed deposition of gold nanoparticles which were again used as seeds for the production of germanium nanostructures. A supercritical CO2 (sc-CO2) technique was successfully used during the production of the germanium nanostructures.

A benchmark comparison between reconfigurable, intelligent and autonomous wireless inertial measurement and photonic technologies in rehabilitation

Advanced sensory systems address a number of major obstacles towards the provision for cost effective and proactive rehabilitation. Many of these systems employ technologies such as high-speed video or motion capture to generate quantitative measurements. However these solutions are accompanied by some major limitations including extensive set-up and calibration, restriction to indoor use, high cost and time consuming data analysis. Additionally many do not quantify improvement in a rigorous manner for example gait analysis for 5 minutes as opposed to 24 hour ambulatory monitoring. This work addresses these limitations using low cost, wearable wireless inertial measurement as a mobile and minimal infrastructure alternative. In cooperation with healthcare professionals the goal is to design and implement a reconfigurable and intelligent movement capture system. A key component of this work is an extensive benchmark comparison with the 'gold standard' VICON motion capture system.

Metacomputing on clusters augmented with reconfigurable hardware

Accepted Version

Hardware design of cryptographic accelerators

With the rapid growth of the Internet and digital communications, the volume of sensitive electronic transactions being transferred and stored over and on insecure media has increased dramatically in recent years. The growing demand for cryptographic systems to secure this data, across a multitude of platforms, ranging from large servers to small mobile devices and smart cards, has necessitated research into low cost, flexible and secure solutions. As constraints on architectures such as area, speed and power become key factors in choosing a cryptosystem, methods for speeding up the development and evaluation process are necessary. This thesis investigates flexible hardware architectures for the main components of a cryptographic system. Dedicated hardware accelerators can provide significant performance improvements when compared to implementations on general purpose processors. Each of the designs proposed are analysed in terms of speed, area, power, energy and efficiency. Field Programmable Gate Arrays (FPGAs) are chosen as the development platform due to their fast development time and reconfigurable nature. Firstly, a reconfigurable architecture for performing elliptic curve point scalar multiplication on an FPGA is presented. Elliptic curve cryptography is one such method to secure data, offering similar security levels to traditional systems, such as RSA, but with smaller key sizes, translating into lower memory and bandwidth requirements. The architecture is implemented using different underlying algorithms and coordinates for dedicated Double-and-Add algorithms, twisted Edwards algorithms and SPA secure algorithms, and its power consumption and energy on an FPGA measured. Hardware implementation results for these new algorithms are compared against their software counterparts and the best choices for minimum area-time and area-energy circuits are then identified and examined for larger key and field sizes. Secondly, implementation methods for another component of a cryptographic system, namely hash functions, developed in the recently concluded SHA-3 hash competition are presented. Various designs from the three rounds of the NIST run competition are implemented on FPGA along with an interface to allow fair comparison of the different hash functions when operating in a standardised and constrained environment. Different methods of implementation for the designs and their subsequent performance is examined in terms of throughput, area and energy costs using various constraint metrics. Comparing many different implementation methods and algorithms is nontrivial. Another aim of this thesis is the development of generic interfaces used both to reduce implementation and test time and also to enable fair baseline comparisons of different algorithms when operating in a standardised and constrained environment. Finally, a hardware-software co-design cryptographic architecture is presented. This architecture is capable of supporting multiple types of cryptographic algorithms and is described through an application for performing public key cryptography, namely the Elliptic Curve Digital Signature Algorithm (ECDSA). This architecture makes use of the elliptic curve architecture and the hash functions described previously. These components, along with a random number generator, provide hardware acceleration for a Microblaze based cryptographic system. The trade-off in terms of performance for flexibility is discussed using dedicated software, and hardware-software co-design implementations of the elliptic curve point scalar multiplication block. Results are then presented in terms of the overall cryptographic system.

Low power predictable memory and processing architectures

Great demand in power optimized devices shows promising economic potential and draws lots of attention in industry and research area. Due to the continuously shrinking CMOS process, not only dynamic power but also static power has emerged as a big concern in power reduction. Other than power optimization, average-case power estimation is quite significant for power budget allocation but also challenging in terms of time and effort. In this thesis, we will introduce a methodology to support modular quantitative analysis in order to estimate average power of circuits, on the basis of two concepts named Random Bag Preserving and Linear Compositionality. It can shorten simulation time and sustain high accuracy, resulting in increasing the feasibility of power estimation of big systems. For power saving, firstly, we take advantages of the low power characteristic of adiabatic logic and asynchronous logic to achieve ultra-low dynamic and static power. We will propose two memory cells, which could run in adiabatic and non-adiabatic mode. About 90% dynamic power can be saved in adiabatic mode when compared to other up-to-date designs. About 90% leakage power is saved. Secondly, a novel logic, named Asynchronous Charge Sharing Logic (ACSL), will be introduced. The realization of completion detection is simplified considerably. Not just the power reduction improvement, ACSL brings another promising feature in average power estimation called data-independency where this characteristic would make power estimation effortless and be meaningful for modular quantitative average case analysis. Finally, a new asynchronous Arithmetic Logic Unit (ALU) with a ripple carry adder implemented using the logically reversible/bidirectional characteristic exhibiting ultra-low power dissipation with sub-threshold region operating point will be presented. The proposed adder is able to operate multi-functionally.

Secure architectures for pairing based public key cryptography

Along with the growing demand for cryptosystems in systems ranging from large servers to mobile devices, suitable cryptogrophic protocols for use under certain constraints are becoming more and more important. Constraints such as calculation time, area, efficiency and security, must be considered by the designer. Elliptic curves, since their introduction to public key cryptography in 1985 have challenged established public key and signature generation schemes such as RSA, offering more security per bit. Amongst Elliptic curve based systems, pairing based cryptographies are thoroughly researched and can be used in many public key protocols such as identity based schemes. For hardware implementions of pairing based protocols, all components which calculate operations over Elliptic curves can be considered. Designers of the pairing algorithms must choose calculation blocks and arrange the basic operations carefully so that the implementation can meet the constraints of time and hardware resource area. This thesis deals with different hardware architectures to accelerate the pairing based cryptosystems in the field of characteristic two. Using different top-level architectures the hardware efficiency of operations that run at different times is first considered in this thesis. Security is another important aspect of pairing based cryptography to be considered in practically Side Channel Analysis (SCA) attacks. The naively implemented hardware accelerators for pairing based cryptographies can be vulnerable when taking the physical analysis attacks into consideration. This thesis considered the weaknesses in pairing based public key cryptography and addresses the particular calculations in the systems that are insecure. In this case, countermeasures should be applied to protect the weak link of the implementation to improve and perfect the pairing based algorithms. Some important rules that the designers must obey to improve the security of the cryptosystems are proposed. According to these rules, three countermeasures that protect the pairing based cryptosystems against SCA attacks are applied. The implementations of the countermeasures are presented and their performances are investigated.

Energy storage: battery materials and architectures at the nanoscale

Enterprise Ireland (Project CFTD07325). European Commission (EU Framework 7 project Nanofunction, (Beyond CMOS Nanodevices for Adding Functionalities to CMOS) www.Nanofunction.eu EU ICT Network of Excellence, Grant No.257375)

A planar reconfigurable linear rigid-body motion linkage with two operation modes

A planar reconfigurable linear (also rectilinear) rigid-body motion linkage (RLRBML) with two operation modes, that is, linear rigid-body motion mode and lockup mode, is presented using only R (revolute) joints. The RLRBML does not require disassembly and external intervention to implement multi-task requirements. It is created via combining a Robert’s linkage and a double parallelogram linkage (with equal lengths of rocker links) arranged in parallel, which can convert a limited circular motion to a linear rigid-body motion without any reference guide way. This linear rigid-body motion is achieved since the double parallelogram linkage can guarantee the translation of the motion stage, and Robert’s linkage ensures the approximate straight line motion of its pivot joint connecting to the double parallelogram linkage. This novel RLRBML is under the linear rigid-body motion mode if the four rocker links in the double parallelogram linkage are not parallel. The motion stage is in the lockup mode if all of the four rocker links in the double parallelogram linkage are kept parallel in a tilted position (but the inner/outer two rocker links are still parallel). In the lockup mode, the motion stage of the RLRBML is prohibited from moving even under power off, but the double parallelogram linkage is still moveable for its own rotation application. It is noted that further RLRBMLs can be obtained from the above RLRBML by replacing Robert’s linkage with any other straight line motion linkage (such as Watt’s linkage). Additionally, a compact RLRBML and two single-mode linear rigid-body motion linkages are presented.

Chemical approaches for doping nanodevice architectures

Advanced doping technologies are key for the continued scaling of semiconductor devices and the maintenance of device performance beyond the 14 nm technology node. Due to limitations of conventional ion-beam implantation with thin body and 3D device geometries, techniques which allow precise control over dopant diffusion and concentration, in addition to excellent conformality on 3D device surfaces, are required. Spin-on doping has shown promise as a conventional technique for doping new materials, particularly through application with other dopant methods, but may not be suitable for conformal doping of nanostructures. Additionally, residues remain after most spin-on-doping processes which are often difficult to remove. In-situ doping of nanostructures is especially common for bottom-up grown nanostructures but problems associated with concentration gradients and morphology changes are commonly experienced. Monolayer doping (MLD) has been shown to satisfy the requirements for extended defect-free, conformal and controllable doping on many materials ranging from traditional silicon and germanium devices to emerging replacement materials such as III-V compounds but challenges still remain, especially with regard to metrology and surface chemistry at such small feature sizes. This article summarises and critically assesses developments over the last number of years regarding the application of gas and solution phase techniques to dope silicon-, germanium- and III-V-based materials and nanostructures to obtain shallow diffusion depths coupled with high carrier concentrations and abrupt junctions.

SDN enabled dynamically reconfigurable high capacity optical access architecture for converged services

Dynamically reconfigurable time-division multiplexing (TDM) dense wavelength division multiplexing (DWDM) long-reach passive optical networks (PONs) can support the reduction of nodes and network interfaces by enabling a fully meshed flat optical core. In this paper we demonstrate the flexibility of the TDM-DWDM PON architecture, which can enable the convergence of multiple service types on a single physical layer. Heterogeneous services and modulation formats, i.e. residential 10G PON channels, business 100G dedicated channel and wireless fronthaul, are demonstrated co-existing on the same long reach TDM-DWDM PON system, with up to 100km reach, 512 users and emulated system load of 40 channels, employing amplifier nodes with either erbium doped fiber amplifiers (EDFAs) or semiconductor optical amplifiers (SOAs). For the first time end-to-end software defined networking (SDN) management of the access and core network elements is also implemented and integrated with the PON physical layer in order to demonstrate two service use cases: a fast protection mechanism with end-to-end service restoration in the case of a primary link failure; and dynamic wavelength allocation (DWA) in response to an increased traffic demand.