A study of silicon and germanium junctionless transistors

Technology boosters, such as strain, HKMG and FinFET, have been introduced into semiconductor industry to extend Moore’s law beyond 130 nm technology nodes. New device structures and channel materials are highly demanded to keep performance enhancement when the device scales beyond 22 nm. In this work, the properties and feasibility of the proposed Junctionless transistor (JNT) have been evaluated for both Silicon and Germanium channels. The performance of Silicon JNTs with 22 nm gate length have been characterized at elevated temperature and stressed conditions. Furthermore, steep Subthreshold Slopes (SS) in JNT and IM devices are compared. It is observed that the floating body in JNT is relatively dynamic comparing with that in IM devices and proper design of the device structure may further reduce the VD for a sub- 60 mV/dec subthreshold slope. Diode configuration of the JNT has also been evaluated, which demonstrates the first diode without junctions. In order to extend JNT structure into the high mobility material Germanium (Ge), a full process has been develop for Ge JNT. Germanium-on-Insulator (GeOI) wafers were fabricated using Smart-Cut with low temperature direct wafer bonding method. Regarding the lithography and pattern transfer, a top-down process of sub-50-nm width Ge nanowires is developed in this chapter and Ge nanowires with 35 nm width and 50 nm depth are obtained. The oxidation behaviour of Ge by RTO has been investigated and high-k passivation scheme using thermally grown GeO2 has been developed. With all developed modules, JNT with Ge channels have been fabricated by the CMOScompatible top-down process. The transistors exhibit the lowest subthreshold slope to date for Ge JNT. The devices with a gate length of 3 μm exhibit a SS of 216 mV/dec with an ION/IOFF current ratio of 1.2×103 at VD = -1 V and DIBL of 87 mV/V.

Resist-substrate interface tailoring for generating high density arrays of Ge and Bi2Se3 nanowires by electron beam lithography

The authors report a chemical process to remove the native oxide on Ge and Bi2Se3 crystals, thus facilitating high-resolution electron beam lithography (EBL) on their surfaces using a hydrogen silsesquioxane (HSQ) resist. HSQ offers the highest resolution of all the commercially available EBL resists. However, aqueous HSQ developers such as NaOH and tetramethylammonium hydroxide have thus far prevented the fabrication of high-resolution structures via the direct application of HSQ to Ge and Bi2Se3, due to the solubility of components of their respective native oxides in these strong aqueous bases. Here we provide a route to the generation of ordered, high-resolution, high-density Ge and Bi2Se3 nanostructures with potential applications in microelectronics, thermoelectric, and photonics devices.                         

TPEA good practice guide: lessons for cross-border MSP from transboundary planning in the European Atlantic

This Good Practice Guide is the outcome of a project co-funded by the European Commission (DG Mare) called Transboundary Planning in the European Atlantic (TPEA), which ran from December 2012 to May 2014. The aim of the project was to demonstrate approaches to transboundary maritime spatial planning (MSP) in the European Atlantic region. This is one of a series of projects exploring the opportunities and challenges of carrying out cross-border MSP in Europe’s regional seas, making connections with integrated coastal management (ICM). TPEA focused on two pilot areas: one involving Portugal and Spain and the other Ireland and the United Kingdom. Despite distinct identities in the region relating to different traditions of planning and stages of MSP implementation, TPEA worked towards a commonly-agreed approach to transboundary MSP and developed principles of cross-border working which it is hoped will be of wider benefit. This guide presents these principles, illustrated with examples from the TPEA project.