9 resultados para Polystyrene-b-polyethylene oxide

em CORA - Cork Open Research Archive - University College Cork - Ireland


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The microphase separation of block copolymer (BCP) thin films can afford a simple and cost-effective means to studying nanopattern surfaces, and especially the fabrication of nanocircuitry. However, because of complex interface effects and other complications, their 3D morphology, which is often critical for application, can be more complex than first thought. Here, we describe how emerging microscopic methods may be used to study complex BCP patterns and reveal their rich detail. These methods include helium ion microscopy (HIM) and high resolution x-section transmission electron microscopy (XTEM), and complement conventional secondary electron and atomic force microscopies (SEM and TEM). These techniques reveal that these structures are quite different to what might be expected. We illustrate the advances in the understanding of BCP thin film morphology in several systems, which result from this characterization. The systems described include symmetric, lamellar forming polystyrene-b-polymethylmethacrylate (PS-b-PMMA), cylinder forming polystyrene-b-polydimethylsiloxane (PS-b-PDMS), as well as lamellar and cylinder forming patterns of polystyrene-b-polyethylene oxide (PS-b-PEO) and polystyrene-b-poly-4-vinylpyridine (PS-b-P4VP). Each of these systems exhibits more complex arrangements than might be first thought. Finding and developing techniques whereby complex morphologies, particularly at very small dimensions, can be determined is critical to the practical use of these materials in many applications. The importance of quantifying these complex morphologies has implications for their use in integrated circuit manufacture, where they are being explored as alternative pattern forming methods to conventional UV lithography.

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This thesis details the top-down fabrication of nanostructures on Si and Ge substrates by electron beam lithography (EBL). Various polymeric resist materials were used to create nanopatterns by EBL and Chapter 1 discusses the development characteristics of these resists. Chapter 3 describes the processing parameters, resolution and topographical and structural changes of a new EBL resist known as ‘SML’. A comparison between SML and the standard resists PMMA and ZEP520A was undertaken to determine the suitability of SML as an EBL resist. It was established that SML is capable of high-resolution patterning and showed good pattern transfer capabilities. Germanium is a desirable material for use in microelectronic applications due to a number of superior qualities over silicon. EBL patterning of Ge with high-resolution hydrogen silsesquioxane (HSQ) resist is however difficult due to the presence of native surface oxides. Thus, to combat this problem a new technique for passivating Ge surfaces prior to EBL processes is detailed in Chapter 4. The surface passivation was carried out using simple acids like citric acid and acetic acid. The acids were gentle on the surface and enabled the formation of high-resolution arrays of Ge nanowires using HSQ resist. Chapter 5 details the directed self-assembly (DSA) of block copolymers (BCPs) on EBL patterned Si and, for the very first time, Ge surfaces. DSA of BCPs on template substrates is a promising technology for high volume and cost effective nanofabrication. The BCP employed for this study was poly (styrene-b-ethylene oxide) and the substrates were pre-defined by HSQ templates produced by EBL. The DSA technique resulted into pattern rectification (ordering in BCP) and in pattern multiplication within smaller areas.

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The nanometer range structure produced by thin films of diblock copolymers makes them a great of interest as templates for the microelectronics industry. We investigated the effect of annealing solvents and/or mixture of the solvents in case of symmetric Poly (styrene-block-4vinylpyridine) (PS-b-P4VP) diblock copolymer to get the desired line patterns. In this paper, we used different molecular weights PS-b-P4VP to demonstrate the scalability of such high χ BCP system which requires precise fine-tuning of interfacial energies achieved by surface treatment and that improves the wetting property, ordering, and minimizes defect densities. Bare Silicon Substrates were also modified with polystyrene brush and ethylene glycol self-assembled monolayer in a simple quick reproducible way. Also, a novel and simple in situ hard mask technique was used to generate sub-7nm Iron oxide nanowires with a high aspect ratio on Silicon substrate, which can be used to develop silicon nanowires post pattern transfer.

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Layered metal oxides provide a single-step route to sheathed superlattices of atomic layers of a variety of inorganic materials, where the interlayer spacing and overall layered structure forms the most critical feature in the nanomaterials’ growth and application in electronics, health, and energy storage. We use a combination of computer simulations and experiments to describe the atomic-scale structure, dynamics and energetics of alkanethiol-intercalated layered vanadium oxide-based nanostructures. Molecular dynamics (MD) simulations identify the unusual substrate-constrained packing of the alkanethiol surfactant chains along each V2O5 (010) face that combines with extensive interdigitation between chains on opposing faces to maximize three-dimensional packing in the interlayer regions. The findings are supported by high resolution electron microscopy analyses of synthesized alkanethiol-intercalated vanadium oxide nanostructures, and the preference for this new interdigitated model is clarified using a large set of MD simulations. This dependency stresses the importance of organic–inorganic interactions in layered material systems, the control of which is central to technological applications of flexible hybrid nanomaterials.

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Thin layers of indium tin oxide are widely used as transparent coatings and electrodes in solar energy cells, flat-panel displays, antireflection coatings, radiation protection and lithium-ion battery materials, because they have the characteristics of low resistivity, strong absorption at ultraviolet wavelengths, high transmission in the visible, high reflectivity in the far-infrared and strong attenuation in the microwave region. However, there is often a trade-off between electrical conductivity and transparency at visible wavelengths for indium tin oxide and other transparent conducting oxides. Here, we report the growth of layers of indium tin oxide nanowires that show optimum electronic and photonic properties and demonstrate their use as fully transparent top contacts in the visible to near-infrared region for light-emitting devices.

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We report the detailed characterization of high quality vanadium oxide (VOx) nanotubes (NTs) and highlight the zipping of adjacent vanadate layers in such NTs formed on remarkable nanourchin structures. These nanostructures consist of high-density spherical radial arrays of NTs. The results evidence vanadate NTs with unprecedented uniformity and evidences the first report of vanadate atomic layer zipping. The NTs are ∼2 μm in length with inner diameters of 20-30 nm. The tube walls comprise scrolled triplet-layers of vanadate intercalated with organic surfactant. Such high-volume structures might be useful as open-access electrolyte scaffolds for lithium insertion-based charge storage devices.

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We present a comparative structural–vibrational study of nanostructured systems of V2O5: nano-urchin (VONURs) which are spherical structures composed of a radially oriented array of VOx nanotubes (VOx-NTs) with a volumetric density of ∼40 sr–1, and vanadium oxide nanorods (VOx-NRDs) with an average length of ∼100 nm. The Raman scattering spectrum of the nano-urchin exhibits a band at 1014 cm–1 related to the distorted gamma conformation of the vanadium pentoxide (γ-V5+). The infrared vibrational spectra of the nanorods sample also exhibit a distorted laminar V2O5 structure with evidence observed for quadravalent V4+ species at 921 cm–1.

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This work looks at the effect on mid-gap interface state defect density estimates for In0.53Ga0.47As semiconductor capacitors when different AC voltage amplitudes are selected for a fixed voltage bias step size (100 mV) during room temperature only electrical characterization. Results are presented for Au/Ni/Al2O3/In0.53Ga0.47As/InP metal–oxide–semiconductor capacitors with (1) n-type and p-type semiconductors, (2) different Al2O3 thicknesses, (3) different In0.53Ga0.47As surface passivation concentrations of ammonium sulphide, and (4) different transfer times to the atomic layer deposition chamber after passivation treatment on the semiconductor surface—thereby demonstrating a cross-section of device characteristics. The authors set out to determine the importance of the AC voltage amplitude selection on the interface state defect density extractions and whether this selection has a combined effect with the oxide capacitance. These capacitors are prototypical of the type of gate oxide material stacks that could form equivalent metal–oxide–semiconductor field-effect transistors beyond the 32 nm technology node. The authors do not attempt to achieve the best scaled equivalent oxide thickness in this work, as our focus is on accurately extracting device properties that will allow the investigation and reduction of interface state defect densities at the high-k/III–V semiconductor interface. The operating voltage for future devices will be reduced, potentially leading to an associated reduction in the AC voltage amplitude, which will force a decrease in the signal-to-noise ratio of electrical responses and could therefore result in less accurate impedance measurements. A concern thus arises regarding the accuracy of the electrical property extractions using such impedance measurements for future devices, particularly in relation to the mid-gap interface state defect density estimated from the conductance method and from the combined high–low frequency capacitance–voltage method. The authors apply a fixed voltage step of 100 mV for all voltage sweep measurements at each AC frequency. Each of these measurements is repeated 15 times for the equidistant AC voltage amplitudes between 10 mV and 150 mV. This provides the desired AC voltage amplitude to step size ratios from 1:10 to 3:2. Our results indicate that, although the selection of the oxide capacitance is important both to the success and accuracy of the extraction method, the mid-gap interface state defect density extractions are not overly sensitive to the AC voltage amplitude employed regardless of what oxide capacitance is used in the extractions, particularly in the range from 50% below the voltage sweep step size to 50% above it. Therefore, the use of larger AC voltage amplitudes in this range to achieve a better signal-to-noise ratio during impedance measurements for future low operating voltage devices will not distort the extracted interface state defect density.

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Fabrication of nanoscale patterns through the bottom-up approach of self-assembly of phase-separated block copolymers (BCP) holds promise for nanoelectronics applications. For lithographic applications, it is useful to vary the morphology of BCPs by monitoring various parameters to make “from lab to fab” a reality. Here I report on the solvent annealing studies of lamellae forming polystyrene-blockpoly( 4-vinylpyridine) (PS-b-P4VP). The high Flory-Huggins parameter (χ = 0.34) of PS-b-P4VP makes it an ideal BCP system for self-assembly and template fabrication in comparison to other BCPs. Different molecular weights of symmetric PS-b-P4VP BCPs forming lamellae patterns were used to produce nanostructured thin films by spin-coating from mixture of toluene and tetrahydrofuran(THF). In particular, the morphology change from micellar structures to well-defined microphase separated arrangements is observed. Solvent annealing provides a better alternative to thermal treatment which often requires long annealing periods. The choice of solvent (single and dual solvent exposure) and the solvent annealing conditions have significant effects on the morphology of films and it was found that a block neutral solvent was required to realize vertically aligned PS and P4VP lamellae. Here, we have followed the formation of microdomain structures with time development at different temperatures by atomic force microscopy (AFM). The highly mobilized chains phase separate quickly due to high Flory-Huggins (χ) parameter. Ultra-small feature size (~10 nm pitch size) nanopatterns were fabricated by using low molecular weight PSb- P4VP (PS and P4VP blocks of 3.3 and 3.1 kg mol-1 respectively). However, due to the low etch contrast between the blocks, pattern transfer of the BCP mask is very challenging. To overcome the etch contrast problem, a novel and simple in-situ hard mask technology is used to fabricate the high aspect ratio silicon nanowires. The lamellar structures formed after self-assembly of phase separated PS-b-P4VP BCPs were used to fabricate iron oxide nanowires which acted as hard mask material to facilitate the pattern transfer into silicon and forming silicon nanostructures. The semiconductor and optical industries have shown significant interest in two dimensional (2D) molybdenum disulphide (MoS2) as a potential device material due to its low band gap and high mobility. However, current methods for its synthesis are not ‘fab’ friendly and require harsh environments and processes. Here, I also report a novel method to prepare MoS2 layered structures via self-assembly of a PS-b-P4VP block copolymer system. The formation of the layered MoS2 was confirmed by XPS, Raman spectroscopy and high resolution transmission electron microscopy.