Assessing charge contribution from thermally treated Ni foam as current collectors for Li-ion batteries

In this report we have investigated the use of Ni foam substrates as anode current collectors for Li-ion batteries. As the majority of reports in the literature focus on hydrothermal formation of materials on Ni foam followed by a high temperature anneal/oxidation step, we probed the fundamental electrochemical responses of as received Ni foam substrates and those subjected to heating at 100°C, 300°C and 450°C. Through cyclic voltammetry and galvanostatic testing, it is shown that the as received and 100°C annealed Ni foam show negligible electrochemical activity. However, Ni foams heated to higher temperature showed substantial electrochemical contributions which may lead to inflated capacities and incorrect interpretations of CV responses for samples subjected to high temperature anneals. XRD, XPS and SEM analyses clearly illustrate that the formation of electrochemically active NiO nanoparticles on the surface of the foam is responsible for this behavior. To further investigate the contribution of the oxidized Ni foam to the overall electrochemical response, we formed Co3O4 nanoflowers directly on Ni foam at 450°C and showed that the resulting electrochemical response was dominated by NiO after the first 10 charge/discharge cycles. This report highlights the importance of assessing current collector activity for active materials grown on transition metal foam current collectors for Li-ion applications.

The structural conversion from α-AgVO3 to β-AgVO3: Ag nanoparticle decorated nanowires with application as cathode materials for Li-ion batteries

The majority of electrode materials in batteries and related electrochemical energy storage devices are fashioned into slurries via the addition of a conductive additive and a binder. However, aggregation of smaller diameter nanoparticles in current generation electrode compositions can result in non-homogeneous active materials. Inconsistent slurry formulation may lead to inconsistent electrical conductivity throughout the material, local variations in electrochemical response, and the overall cell performance. Here we demonstrate the hydrothermal preparation of Ag nanoparticle (NP) decorated α-AgVO3 nanowires (NWs) and their conversion to tunnel structured β-AgVO3 NWs by annealing to form a uniform blend of intercalation materials that are well connected electrically. The synthesis of nanostructures with chemically bound conductive nanoparticles is an elegant means to overcome the intrinsic issues associated with electrode slurry production, as wire-to-wire conductive pathways are formed within the overall electrode active mass of NWs. The conversion from α-AgVO3 to β-AgVO3 is explained in detail through a comprehensive structural characterization. Meticulous EELS analysis of β-AgVO3 NWs offers insight into the true β-AgVO3 structure and how the annealing process facilitates a higher surface coverage of Ag NPs directly from ionic Ag content within the α-AgVO3 NWs. Variations in vanadium oxidation state across the surface of the nanowires indicate that the β-AgVO3 NWs have a core–shell oxidation state structure, and that the vanadium oxidation state under the Ag NP confirms a chemically bound NP from reduction of diffused ionic silver from the α-AgVO3 NWs core material. Electrochemical comparison of α-AgVO3 and β-AgVO3 NWs confirms that β-AgVO3 offers improved electrochemical performance. An ex situ structural characterization of β-AgVO3 NWs after the first galvanostatic discharge and charge offers new insight into the Li+ reaction mechanism for β-AgVO3. Ag+ between the van der Waals layers of the vanadium oxide is reduced during discharge and deposited as metallic Ag, the vacant sites are then occupied by Li+.

Modifying germanium nanowires for future devices: an in situ TEM study

Germanium was of great interest in the 1950’s when it was used for the first transistor device. However, due to the water soluble and unstable oxide it was surpassed by silicon. Today, as device dimensions are shrinking the silicon oxide is no longer suitable due to gate leakage and other low-κ dielectrics such as Al2O3 and HfO2 are being used. Germanium (Ge) is a promising material to replace or integrate with silicon (Si) to continue the trend of Moore’s law. Germanium has better intrinsic mobilities than silicon and is also silicon fab compatible so it would be an ideal material choice to integrate into silicon-based technologies. The progression towards nanoelectronics requires a lot of in depth studies. Dynamic TEM studies allow observations of reactions to allow a better understanding of mechanisms and how an external stimulus may affect a material/structure. This thesis details in situ TEM experiments to investigate some essential processes for germanium nanowire (NW) integration into nanoelectronic devices; i.e. doping and Ohmic contact formation. Chapter 1 reviews recent advances in dynamic TEM studies on semiconductor (namely silicon and germanium) nanostructures. The areas included are nanowire/crystal growth, germanide/silicide formation, irradiation, electrical biasing, batteries and strain. Chapter 2 details the study of ion irradiation and the damage incurred in germanium nanowires. An experimental set-up is described to allow for concurrent observation in the TEM of a nanowire following sequential ion implantation steps. Grown nanowires were deposited on a FIB labelled SiN membrane grid which facilitated HRTEM imaging and facile navigation to a specific nanowire. Cross sections of irradiated nanowires were also performed to evaluate the damage across the nanowire diameter. Experiments were conducted at 30 kV and 5 kV ion energies to study the effect of beam energy on nanowires of varied diameters. The results on nanowires were also compared to the damage profile in bulk germanium with both 30 kV and 5 kV ion beam energies. Chapter 3 extends the work from chapter 2 whereby nanowires are annealed post ion irradiation. In situ thermal annealing experiments were conducted to observe the recrystallization of the nanowires. A method to promote solid phase epitaxial growth is investigated by irradiating only small areas of a nanowire to maintain a seed from which the epitaxial growth can initiate. It was also found that strain in the nanowire greatly effects defect formation and random nucleation and growth. To obtain full recovery of the crystal structure of a nanowire, a stable support which reduces strain in the nanowire is essential as well as containing a seed from which solid phase epitaxial growth can initiate. Chapter 4 details the study of nickel germanide formation in germanium nanostructures. Rows of EBL (electron beam lithography) defined Ni-capped germanium nanopillars were extracted in FIB cross sections and annealed in situ to observe the germanide formation. Chapter 5 summarizes the key conclusions of each chapter and discusses an outlook on the future of germanium nanowire studies to facilitate their future incorporation into nanodevices.

Average-case analysis of power consumption in embedded systems

Power efficiency is one of the most important constraints in the design of embedded systems since such systems are generally driven by batteries with limited energy budget or restricted power supply. In every embedded system, there are one or more processor cores to run the software and interact with the other hardware components of the system. The power consumption of the processor core(s) has an important impact on the total power dissipated in the system. Hence, the processor power optimization is crucial in satisfying the power consumption constraints, and developing low-power embedded systems. A key aspect of research in processor power optimization and management is “power estimation”. Having a fast and accurate method for processor power estimation at design time helps the designer to explore a large space of design possibilities, to make the optimal choices for developing a power efficient processor. Likewise, understanding the processor power dissipation behaviour of a specific software/application is the key for choosing appropriate algorithms in order to write power efficient software. Simulation-based methods for measuring the processor power achieve very high accuracy, but are available only late in the design process, and are often quite slow. Therefore, the need has arisen for faster, higher-level power prediction methods that allow the system designer to explore many alternatives for developing powerefficient hardware and software. The aim of this thesis is to present fast and high-level power models for the prediction of processor power consumption. Power predictability in this work is achieved in two ways: first, using a design method to develop power predictable circuits; second, analysing the power of the functions in the code which repeat during execution, then building the power model based on average number of repetitions. In the first case, a design method called Asynchronous Charge Sharing Logic (ACSL) is used to implement the Arithmetic Logic Unit (ALU) for the 8051 microcontroller. The ACSL circuits are power predictable due to the independency of their power consumption to the input data. Based on this property, a fast prediction method is presented to estimate the power of ALU by analysing the software program, and extracting the number of ALU-related instructions. This method achieves less than 1% error in power estimation and more than 100 times speedup in comparison to conventional simulation-based methods. In the second case, an average-case processor energy model is developed for the Insertion sort algorithm based on the number of comparisons that take place in the execution of the algorithm. The average number of comparisons is calculated using a high level methodology called MOdular Quantitative Analysis (MOQA). The parameters of the energy model are measured for the LEON3 processor core, but the model is general and can be used for any processor. The model has been validated through the power measurement experiments, and offers high accuracy and orders of magnitude speedup over the simulation-based method.