Towards the design of monolithic decoupled XYZ compliant parallel mechanisms for multi-function applications

This paper deals with the monolithic decoupled XYZ compliant parallel mechanisms (CPMs) for multi-function applications, which can be fabricated monolithically without assembly and has the capability of kinetostatic decoupling. At first, the conceptual design of monolithic decoupled XYZ CPMs is presented using identical spatial compliant multi-beam modules based on a decoupled 3-PPPR parallel kinematic mechanism. Three types of applications: motion/positioning stages, force/acceleration sensors and energy harvesting devices are described in principle. The kinetostatic and dynamic modelling is then conducted to capture the displacements of any stage under loads acting at any stage and the natural frequency with the comparisons with FEA results. Finally, performance characteristics analysis for motion stage applications is detailed investigated to show how the change of the geometrical parameter can affect the performance characteristics, which provides initial optimal estimations. Results show that the smaller thickness of beams and larger dimension of cubic stages can improve the performance characteristics excluding natural frequency under allowable conditions. In order to improve the natural frequency characteristic, a stiffness-enhanced monolithic decoupled configuration that is achieved through employing more beams in the spatial modules or reducing the mass of each cubic stage mass can be adopted. In addition, an isotropic variation with different motion range along each axis and same payload in each leg is proposed. The redundant design for monolithic fabrication is introduced in this paper, which can overcome the drawback of monolithic fabrication that the failed compliant beam is difficult to replace, and extend the CPM’s life.

CUBEs: decoupled, compact, and monolithic spatial translational compliant parallel manipulators

This paper deals with the conceptual design of decoupled, compact, and monolithic XYZ compliant parallel manipulators (CPMs): CUBEs. Position spaces of compliant P (P: prismatic) joints are first discussed, which are represented by circles about the translational directions. A design method of monolithic XYZ CPMs is then proposed in terms of both the kinematic substitution method and the position spaces. Three types of monolithic XYZ CPMs are finally designed using the proposed method with the help of three classes of kinematical decoupled 3-DOF (degree of freedom) translational parallel mechanisms (TPMs). These monolithic XYZ CPMs include a 3-PPP XYZ CPM composed of identical parallelogram modules (a previously reported design), a novel 3-PPPR (R: revolute) XYZ CPM composed of identical compliant four-beam modules, and a novel 3-PPPRR XYZ CPM. The latter two monolithic designs also have extended lives. It is shown that the proposed design method can be used to design other decoupled and compact XYZ CPMs by using the concept of position spaces, and the resulting XYZ CPM is the most compact one when the fixed ends of the three actuated compliant P joints thereof overlap.

Semiconductor nanowire fabrication via bottom-up & top-down paradigms

Semiconductor nanowires are pseudo 1-D structures where the magnitude of the semiconducting material is confined to a length of less than 100 nm in two dimensions. Semiconductor nanowires have a vast range of potential applications, including electronic (logic devices, diodes), photonic (laser, photodetector), biological (sensors, drug delivery), energy (batteries, solar cells, thermoelectric generators), and magnetic (spintronic, memory) devices. Semiconductor nanowires can be fabricated by a range of methods which can be categorised into one of two paradigms, bottom-up or top-down. Bottom-up processes can be defined as those where structures are assembled from their sub-components in an additive fashion. Top-down fabrication strategies use sculpting or etching to carve structures from a larger piece of material in a subtractive fashion. This seminar will detail a number of novel routes to fabricate semiconductor nanowires by both bottom-up and top-down paradigms. Firstly, a novel bottom-up route to fabricate Ge nanowires with controlled diameter distributions in the sub-20 nm regime will be described. This route details nanowire synthesis and diameter control in the absence of a foreign seed metal catalyst. Additionally a top-down route to nanowire array fabrication will be detailed outlining the importance of surface chemistry in high-resolution electron beam lithography (EBL) using hydrogen silsesquioxane (HSQ) on Ge and Bi2Se3 surfaces. Finally, a process will be described for the directed self-assembly of a diblock copolymer (PS-b-PDMS) using an EBL defined template. This section will also detail a route toward selective template sidewall wetting of either block in the PS-b-PDMS system, through tailored functionalisation of the template and substrate surfaces.

Fabrication and characterisation of semiconductor nanowires and metal interconnects

One-dimensional semiconductor nanowires are considered to be promising materials for future nanoelectronic applications. However, before these nanowires can be integrated into such applications, a thorough understanding of their growth behaviour is necessary. In particular, methods that allow the control over nanowire growth are deemed especially important as it is these methods that will enable the control of nanowire dimensions such as length and diameter (high aspect ratios). The production of nanowires with high-aspect ratios is vital in order to take advantage of the unique properties experienced at the nanoscale, thus allowing us to maximise their use in devices. Additionally, the development of low-resistivity interconnects is desirable in order to connect such nanowires in multi-nanowire components. Consequently, this thesis aims to discuss the synthesis and characterisation of germanium (Ge) nanowires and platinum (Pt) interconnects. Particular emphasis is placed on manipulating the nanowire growth kinetics to produce high aspect ratio structures. The discussion of Pt interconnects focuses on the development of low-resistivity devices and the electrical and structural analysis of those devices. Chapter 1 reviews the most critical aspects of Ge nanowire growth which must be understood before they can be integrated into future nanodevices. These features include the synthetic methods employed to grow Ge nanowires, the kinetic and thermodynamic aspects of their growth and nanowire morphology control. Chapter 2 outlines the experimental methods used to synthesise and characterise Ge nanowires as well as the methods used to fabricate and analyse Pt interconnects. Chapter 3 discusses the control of Ge nanowire growth kinetics via the manipulation of the supersaturation of Ge in the Au/Ge binary alloy system. This is accomplished through the use of bi-layer films, which pre-form Au/Ge alloy catalysts before the introduction of the Ge precursor. The growth from these catalysts is then compared with Ge nanowire growth from standard elemental Au seeds. Nanowires grown from pre-formed Au/Ge alloy seeds demonstrate longer lengths and higher growth rates than those grown from standard Au seeds. In-situ TEM heating on the Au/Ge bi-layer films is used to support the growth characteristics observed. Chapter 4 extends the work of chapter 3 by utilising Au/Ag/Ge tri-layer films to enhance the growth rates and lengths of Ge nanowires. These nanowires are grown from Au/Ag/Ge ternary alloy catalysts. Once again, the supersaturation is influenced, only this time it is through the simultaneous manipulation of both the solute concentration and equilibrium concentration of Ge in the Au/Ag/Ge ternary alloy system. The introduction of Ag to the Au/Ge binary alloy lowers the equilibrium concentration, thus increasing the nanowire growth rate and length. Nanowires with uniform diameters were obtained via synthesis from AuxAg1-x alloy nanoparticles. Manifestation of the Gibbs-Thomson effect, resulting from the dependence of the mean nanowire length as a function of diameter, was observed for all of the nanowires grown from the AuxAg1-x nanoparticles. Finally, in-situ TEM heating was used to support the nanowire growth characteristics. Chapter 5 details the fabrication and characterisation of Pt interconnects deposited by electron beam induced deposition of two different precursors. The fabrication is conducted inside a dual beam FIB. The electrical and structural characteristics of interconnects deposited from a standard organometallic precursor and a novel carbon-free precursor are compared. The electrical performance of the carbon-free interconnects is shown to be superior to that of the organometallic devices and this is correlated to the structural composition of both interconnects via in-situ TEM heating and HAADF-STEM analysis. Annealing of the interconnects is carried out under two different atmospheres in order to reduce the electrical resistivity even further. Finally, chapter 6 presents some important conclusions and summarises each of the previous chapters.

Fabrication, characterisation and electroanalysis at 1-dimensional nanostructures

Integrated nanowire electrodes that permit direct, sensitive and rapid electrochemical based detection of chemical and biological species are a powerful emerging class of sensor devices. As critical dimensions of the electrodes enter the nanoscale, radial analyte diffusion profiles to the electrode dominate with a corresponding enhancement in mass transport, steady-state sigmoidal voltammograms, low depletion of target molecules and faster analysis. To optimise these sensors it is necessary to fully understand the factors that influence performance limits including: electrode geometry, electrode dimensions, electrode separation distances (within nanowire arrays) and diffusional mass transport. Therefore, in this thesis, theoretical simulations of analyte diffusion occurring at a variety of electrode designs were undertaken using Comsol Multiphysics®. Sensor devices were fabricated and corresponding experiments were performed to challenge simulation results. Two approaches for the fabrication and integration of metal nanowire electrodes are presented: Template Electrodeposition and Electron-Beam Lithography. These approaches allow for the fabrication of nanowires which may be subsequently integrated at silicon chip substrates to form fully functional electrochemical devices. Simulated and experimental results were found to be in excellent agreement validating the simulation model. The electrochemical characteristics exhibited by nanowire electrodes fabricated by electronbeam lithography were directly compared against electrochemical performance of a commercial ultra-microdisc electrode. Steady-state cyclic voltammograms in ferrocenemonocarboxylic acid at single ultra-microdisc electrodes were observed at low to medium scan rates (≤ 500 mV.s-1). At nanowires, steady-state responses were observed at ultra-high scan rates (up to 50,000 mV.s-1), thus allowing for much faster analysis (20 ms). Approaches for elucidating faradaic signal without the requirement for background subtraction were also developed. Furthermore, diffusional process occurring at arrays with increasing inter-electrode distance and increasing number of nanowires were explored. Diffusion profiles existing at nanowire arrays were simulated with Comsol Multiphysics®. A range of scan rates were modelled, and experiments were undertaken at 5,000 mV.s-1 since this allows rapid data capture required for, e.g., biomedical, environmental and pharmaceutical diagnostic applications.

Photonic integrated circuits for the generation of coherent optical signals

The demand for optical bandwidth continues to increase year on year and is being driven primarily by entertainment services and video streaming to the home. Current photonic systems are coping with this demand by increasing data rates through faster modulation techniques, spectrally efficient transmission systems and by increasing the number of modulated optical channels per fibre strand. Such photonic systems are large and power hungry due to the high number of discrete components required in their operation. Photonic integration offers excellent potential for combining otherwise discrete system components together on a single device to provide robust, power efficient and cost effective solutions. In particular, the design of optical modulators has been an area of immense interest in recent times. Not only has research been aimed at developing modulators with faster data rates, but there has also a push towards making modulators as compact as possible. Mach-Zehnder modulators (MZM) have proven to be highly successful in many optical communication applications. However, due to the relatively weak electro-optic effect on which they are based, they remain large with typical device lengths of 4 to 7 mm while requiring a travelling wave structure for high-speed operation. Nested MZMs have been extensively used in the generation of advanced modulation formats, where multi-symbol transmission can be used to increase data rates at a given modulation frequency. Such nested structures have high losses and require both complex fabrication and packaging. In recent times, it has been shown that Electro-absorption modulators (EAMs) can be used in a specific arrangement to generate Quadrature Phase Shift Keying (QPSK) modulation. EAM based QPSK modulators have increased potential for integration and can be made significantly more compact than MZM based modulators. Such modulator designs suffer from losses in excess of 40 dB, which limits their use in practical applications. The work in this thesis has focused on how these losses can be reduced by using photonic integration. In particular, the integration of multiple lasers with the modulator structure was considered as an excellent means of reducing fibre coupling losses while maximising the optical power on chip. A significant difficultly when using multiple integrated lasers in such an arrangement was to ensure coherence between the integrated lasers. The work investigated in this thesis demonstrates for the first time how optical injection locking between discrete lasers on a single photonic integrated circuit (PIC) can be used in the generation of coherent optical signals. This was done by first considering the monolithic integration of lasers and optical couplers to form an on chip optical power splitter, before then examining the behaviour of a mutually coupled system of integrated lasers. By operating the system in a highly asymmetric coupling regime, a stable phase locking region was found between the integrated lasers. It was then shown that in this stable phase locked region the optical outputs of each laser were coherent with each other and phase locked to a common master laser.

Design, fabrication and characterisation of components for microfluidic enzymatic biofuel cells

The concept of a biofuel cell takes inspiration from the natural capability of biological systems to catalyse the conversion of organic matter with a subsequent release of electrical energy. Enzymatic biofuel cells are intended to mimic the processes occurring in nature in a more controlled and efficient manner. Traditional fuel cells rely on the use of toxic catalysts and are often not easily miniaturizable making them unsuitable as implantable power sources. Biofuel cells however use highly selective protein catalysts and renewable fuels. As energy consumption becomes a global issue, they emerge as important tools for energy generation. The microfluidic platforms developed are intended to maximize the amount of electrical energy extracted from renewable fuels which are naturally abundant in the environment and in biological fluids. Combining microfabrication processes, chemical modification and biological surface patterning these devices are promising candidates for micro-power sources for future life science and electronic applications. This thesis considered four main aspects of a biofuel cell research. Firstly, concept of a miniature compartmentalized enzymatic biofuel cell utilizing simple fuels and operating in static conditions is verified and proves the feasibility of enzyme catalysis in energy conversion processes. Secondly, electrode and microfluidic channel study was performed through theoretical investigations of the flow and catalytic reactions which also improved understanding of the enzyme kinetics in the cell. Next, microfluidic devices were fabricated from cost-effective and disposable polymer materials, using the state-of-the-art micro-processing technologies. Integration of the individual components is difficult and multiple techniques to overcome these problems have been investigated. Electrochemical characterization of gold electrodes modified with Nanoporous Gold Structures is also performed. Finally, two strategies for enzyme patterning and encapsulation are discussed. Several protein catalysts have been effectively immobilized on the surface of commercial and microfabricated electrodes by electrochemically assisted deposition in sol-gel and poly-(o-phenylenediamine) polymer matrices and characterised with confirmed catalytic activity.

Atomic layer deposition of interface control layers for the fabrication of III/V MOS devices

The continued advancement of metal oxide semiconductor field effect transistor (MOSFET) technology has shifted the focus from Si/SiO2 transistors towards high-κ/III-V transistors for high performance, faster devices. This has been necessary due to the limitations associated with the scaling of the SiO2 thickness below ~1 nm and the associated increased leakage current due to direct electron tunnelling through the gate oxide. The use of these materials exhibiting lower effective charge carrier mass in conjunction with the use of a high-κ gate oxide allows for the continuation of device scaling and increases in the associated MOSFET device performance. The high-κ/III-V interface is a critical challenge to the integration of high-κ dielectrics on III-V channels. The interfacial chemistry of the high-κ/III-V system is more complex than Si, due to the nature of the multitude of potential native oxide chemistries at the surface with the resultant interfacial layer showing poor electrical insulating properties when high-κ dielectrics are deposited directly on these oxides. It is necessary to ensure that a good quality interface is formed in order to reduce leakage and interface state defect density to maximise channel mobility and reduce variability and power dissipation. In this work, the ALD growth of aluminium oxide (Al2O3) and hafnium oxide (HfO2) after various surface pre-treatments was carried out, with the aim of improving the high-κ/III-V interface by reducing the Dit – the density of interface defects caused by imperfections such as dangling bonds, dimers and other unsatisfied bonds at the interfaces of materials. A brief investigation was performed into the structural and electrical properties of Al2O3 films deposited on In0.53Ga0.47As at 200 and 300oC via a novel amidinate precursor. Samples were determined to experience a severe nucleation delay when deposited directly on native oxides, leading to diminished functionality as a gate insulator due to largely reduced growth per cycle. Aluminium oxide MOS capacitors were prepared by ALD and the electrical characteristics of GaAs, In0.53Ga0.47As and InP capacitors which had been exposed to pre-pulse treatments from triethyl gallium and trimethyl indium were examined, to determine if self-cleaning reactions similar to those of trimethyl aluminium occur for other alkyl precursors. An improved C-V characteristic was observed for GaAs devices indicating an improved interface possibly indicating an improvement of the surface upon pre-pulsing with TEG, conversely degraded electrical characteristics observed for In0.53Ga0.47As and InP MOS devices after pre-treatment with triethyl gallium and trimethyl indium respectively. The electrical characteristics of Al2O3/In0.53Ga0.47As MOS capacitors after in-situ H2/Ar plasma treatment or in-situ ammonium sulphide passivation were investigated and estimates of interface Dit calculated. The use of plasma reduced the amount of interface defects as evidenced in the improved C-V characteristics. Samples treated with ammonium sulphide in the ALD chamber were found to display no significant improvement of the high-κ/III-V interface. HfO2 MOS capacitors were fabricated using two different precursors comparing the industry standard hafnium chloride process with deposition from amide precursors incorporating a ~1nm interface control layer of aluminium oxide and the structural and electrical properties investigated. Capacitors furnished from the chloride process exhibited lower hysteresis and improved C-V characteristics as compared to that of hafnium dioxide grown from an amide precursor, an indication that no etching of the film takes place using the chloride precursor in conjunction with a 1nm interlayer. Optimisation of the amide process was carried out and scaled samples electrically characterised in order to determine if reduced bilayer structures display improved electrical characteristics. Samples were determined to exhibit good electrical characteristics with a low midgap Dit indicative of an unpinned Fermi level

Fabrication and characterization of doped and porous silicon nanowires as anodes for lithium ion batteries

By using Si(100) with different dopant type (n++-type (As) or p-type (B)), it is shown how metal-assisted chemically (MAC) etched silicon nanowires (Si NWs) can form with rough outer surfaces around a solid NW core for p-type NWs, and a unique, defined mesoporous structure for highly doped n-type NWs. High resolution electron microscopy techniques were used to define the characteristic roughening and mesoporous structure within the NWs and how such structures can form due to a judicious choice of carrier concentration and dopant type. Control of roughness and internal mesoporosity is demonstrated during the formation of Si NWs from highly doped n-type Si(100) during electroless etching through a systematic investigation of etching parameters (etching time, AgNO3 concentration, %HF and temperature). Raman scattering measurements of the transverse optical phonon confirm quantum size effects and phonon scattering in mesoporous wires associated with the etching condition, including quantum confinement effects for the nanocrystallites of Si comprising the internal structure of the mesoporous NWs. Laser power heating of NWs confirms phonon confinement and scattering from internal mesoporosity causing reduced thermal conductivity. The Li+ insertion and extraction characteristics at n-type and p-type Si(100) electrodes with different carrier density and doping type are investigated by cyclic voltammetry and constant current measurements. The insertion and extraction potentials are demonstrated to vary with cycling and the occurrence of an activation effect is shown in n-type electrodes where the charge capacity and voltammetric currents are found to be much higher than p-type electrodes. X-ray photo-electron spectroscopy (XPS) and Raman scattering demonstrate that highly doped n-type Si(100) retains Li as a silicide and converts to an amorphous phase as a two-step phase conversion process. The findings show the succinct dependence of Li insertion and extraction processes for uniformly doped Si(100) single crystals and how the doping type and its effect on the semiconductor-solution interface dominate Li insertion and extraction, composition, crystallinity changes and charge capacity. The effect of dopant, doping density and porosity of MAC etched Si NWs are investigated. The CV response is shown to change in area (current density) with increasing NW length and in profile shape with a changing porosity of the Si NWs. The CV response also changes with scan rate indicative of a transition from intercalation or alloying reactions, to pseudocapactive charge storage at higher scan rates and for p-type NWs. SEM and TEM show a change in structure of the NWs after Li insertion and extraction due to expansion and contraction of the Si NWs. Galvanostatic measurements show the cycling behavior and the Coulombic efficiency of the Si NWs in comparison to their bulk counterparts.

Development of block copolymer lithography for device structure fabrication

This thesis investigated well-ordered block copolymer (BCP) thin film characteristics and their use for nanoscale pattern formation using a series of polystyrene-block-polymethylmethacrylate (PS-b-PMMA), polystyrene-blockpolydimethylsiloxane (PS-b-PDMS) and polystyrene-block-poly(ethylene oxide) (PS-b-PEO) systems of various molecular weights. BCP thin films, which act as an ‘on-chip’ etch mask and material templates, are highly promising self-assembling process for future scalable nanolithography. Unlike conventional BCP processing methods, the work in this thesis demonstrates that well-ordered patterns can be achieved in a few seconds compared to several hours by use of a non-conventional microwave assisted technique. As a result, well-ordered BCP nanoscale structures can be developed in industry appropriate periods facilitating their incorporation into current technologies. An optimised and controlled plasma dry etch process was used for successful pattern transfer to the underlying silicon substrate. Long range ordered BCP templates were further modified by selective metal inclusion technique to form a hard mask template towards fabrication of high aspect ratio nanopillars and nanowires. The work described here is centred on how these templates might be used to generate function at substrate surfaces. Herein we describe a number of innovations which might allow their successful uptake in a number of applications.