The development of novel chiral tethers for controlling intramolecular aryl-aryl coupling and their application in the synthesis of gomisin M1 and analogues

The primary focus of this thesis was the development of a novel chiral tether that could be used to control axial chirality around a newly formed aryl-aryl bond, and the extension of this methodology to the model synthesis of gomisin M1. In chapter 1, a review detailing the use of chiral tethers in the synthesis of atropisomers is discussed. The use of a variety of chiral molecules including 1,2-diols, 1,3-diols and other diol-based tethers, as well as amine-based and miscellaneous tethers are detailed. In chapter 2, the rationale behind the design of our novel molecular tethers, along with the subsequent synthesis of three chiral 1,3-diol-based tethers, is outlined. The method by which the enantiopurity of these diols was determined is also reviewed. This chapter also includes the attempted Mitsunobu and intramolecular couplings in the model synthesis of BINOL. Chapter 3 discusses the synthesis of suitable aryl halide substrates, and their employment in the attempted tether-controlled asymmetric model synthesis of gomisin M1. A comprehensive investigation into the attempted intramolecular biaryl coupling of these tethered substrates is also included. The non-stereoselective model synthesis of gomisin M1 is outlined in chapter 4. The installation of the desired biaryl linkage and the subsequent attempted intramolecular McMurry couplings are discussed. The impact of different protecting groups in the molecule on the intramolecular McMurry reaction is also outlined. Chapter 5 details the full experimental procedures, including spectroscopic and analytical data for the compounds prepared during this research.

Average-case analysis of power consumption in embedded systems

Power efficiency is one of the most important constraints in the design of embedded systems since such systems are generally driven by batteries with limited energy budget or restricted power supply. In every embedded system, there are one or more processor cores to run the software and interact with the other hardware components of the system. The power consumption of the processor core(s) has an important impact on the total power dissipated in the system. Hence, the processor power optimization is crucial in satisfying the power consumption constraints, and developing low-power embedded systems. A key aspect of research in processor power optimization and management is “power estimation”. Having a fast and accurate method for processor power estimation at design time helps the designer to explore a large space of design possibilities, to make the optimal choices for developing a power efficient processor. Likewise, understanding the processor power dissipation behaviour of a specific software/application is the key for choosing appropriate algorithms in order to write power efficient software. Simulation-based methods for measuring the processor power achieve very high accuracy, but are available only late in the design process, and are often quite slow. Therefore, the need has arisen for faster, higher-level power prediction methods that allow the system designer to explore many alternatives for developing powerefficient hardware and software. The aim of this thesis is to present fast and high-level power models for the prediction of processor power consumption. Power predictability in this work is achieved in two ways: first, using a design method to develop power predictable circuits; second, analysing the power of the functions in the code which repeat during execution, then building the power model based on average number of repetitions. In the first case, a design method called Asynchronous Charge Sharing Logic (ACSL) is used to implement the Arithmetic Logic Unit (ALU) for the 8051 microcontroller. The ACSL circuits are power predictable due to the independency of their power consumption to the input data. Based on this property, a fast prediction method is presented to estimate the power of ALU by analysing the software program, and extracting the number of ALU-related instructions. This method achieves less than 1% error in power estimation and more than 100 times speedup in comparison to conventional simulation-based methods. In the second case, an average-case processor energy model is developed for the Insertion sort algorithm based on the number of comparisons that take place in the execution of the algorithm. The average number of comparisons is calculated using a high level methodology called MOdular Quantitative Analysis (MOQA). The parameters of the energy model are measured for the LEON3 processor core, but the model is general and can be used for any processor. The model has been validated through the power measurement experiments, and offers high accuracy and orders of magnitude speedup over the simulation-based method.