Solid-state synthesis of embedded single-crystal metal oxide and phosphate nanoparticles and in situ crystallization

A new solid state organometallic route to embedded nanoparticle-containing inorganic materials is shown, through pyrolysis of metal-containing derivatives of cyclotriphosphazenes. Pyrolysis in air and at 800 °C of new molecular precursors gives individual single-crystal nanoparticles of SiP2O7, TiO2, P4O7, WP2O7 and SiO2, depending on the precursor used. High resolution transmission electron microscopy investigations reveal, in most cases, perfect single crystals of metal oxides and the first nanostructures of negative thermal expansion metal phosphates with diameters in the range 2–6 nm for all products. While all nanoparticles are new by this method, WP2O7 and SiP2O7 nanoparticles are reported for the first time. In situ recrystallization formation of nanocrystals of SiP2O7 was also observed due to electron beam induced reactions during measurements of the nanoparticulate pyrolytic products SiO2 and P4O7. The possible mechanism for the formation of the nanoparticles at much lower temperatures than their bulk counterparts in both cases is discussed. Degrees of stabilization from the formation of P4O7 affects the nanocrystalline products: nanoparticles are observed for WP2O7, with coalescing crystallization occurring for the amorphous host in which SiP2O7 crystals form as a solid within a solid. The approach allows the simple formation of multimetallic, monometallic, metal-oxide and metal phosphate nanocrystals embedded in an amorphous dielectric. The method and can be extended to nearly any metal capable of successful coordination as an organometallic to allow embedded nanoparticle layers and features to be deposited or written on surfaces for application as high mobility pyrophosphate lithium–ion cathode materials, catalysis and nanocrystal embedded dielectric layers.

Investigation of electrically active defects at the interface of high-k dielectrics and compound semiconductors

As silicon based devices in integrated circuits reach the fundamental limits of dimensional scaling there is growing research interest in the use of high electron mobility channel materials, such as indium gallium arsenide (InGaAs), in conjunction with high dielectric constant (high-k) gate oxides, for Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) based devices. The motivation for employing high mobility channel materials is to reduce power dissipation in integrated circuits while also providing improved performance. One of the primary challenges to date in the field of III-V semiconductors has been the observation of high levels of defect densities at the high-k/III-V interface, which prevents surface inversion of the semiconductor. The work presented in this PhD thesis details the characterization of MOS devices incorporating high-k dielectrics on III-V semiconductors. The analysis examines the effect of modifying the semiconductor bandgap in MOS structures incorporating InxGa1-xAs (x: 0, 0.15. 0.3, 0.53) layers, the optimization of device passivation procedures designed to reduce interface defect densities, and analysis of such electrically active interface defect states for the high-k/InGaAs system. Devices are characterized primarily through capacitance-voltage (CV) and conductance-voltage (GV) measurements of MOS structures both as a function of frequency and temperature. In particular, the density of electrically active interface states was reduced to the level which allowed the observation of true surface inversion behavior in the In0.53Ga0.47As MOS system. This was achieved by developing an optimized (NH4)2S passivation, minimized air exposure, and atomic layer deposition of an Al2O3 gate oxide. An extraction of activation energies allows discrimination of the mechanisms responsible for the inversion response. Finally a new approach is described to determine the minority carrier generation lifetime and the oxide capacitance in MOS structures. The method is demonstrated for an In0.53Ga0.47As system, but is generally applicable to any MOS structure exhibiting a minority carrier response in inversion.

Design principles for maximizing photovoltage in metal-oxide-protected water-splitting photoanodes

Metal oxide protection layers for photoanodes may enable the development of large-scale solar fuel and solar chemical synthesis, but the poor photovoltages often reported so far will severely limit their performance. Here we report a novel observation of photovoltage loss associated with a charge extraction barrier imposed by the protection layer, and, by eliminating it, achieve photovoltages as high as 630mV, the maximum reported so far for water-splitting silicon photoanodes. The loss mechanism is systematically probed in metal-insulator-semiconductor Schottky junction cells compared to buried junction p(+) n cells, revealing the need to maintain a characteristic hole density at the semiconductor/insulator interface. A leaky-capacitor model related to the dielectric properties of the protective oxide explains this loss, achieving excellent agreement with the data. From these findings, we formulate design principles for simultaneous optimization of built-in field, interface quality, and hole extraction to maximize the photovoltage of oxide-protected water-splitting anodes.