Engineering interfacial silicon dioxide for improved metal-insulator-semiconductor silicon photoanode water splitting performance

Silicon photoanodes protected by atomic layer deposited (ALD) TiO2 show promise as components of water splitting devices that may enable the large-scale production of solar fuels and chemicals. Minimizing the resistance of the oxide corrosion protection layer is essential for fabricating efficient devices with good fill factor. Recent literature reports have shown that the interfacial SiO2 layer, interposed between the protective ALD-TiO2 and the Si anode, acts as a tunnel oxide that limits hole conduction from the photoabsorbing substrate to the surface oxygen evolution catalyst. Herein, we report a significant reduction of bilayer resistance, achieved by forming stable, ultrathin (<1.3 nm) SiO2 layers, allowing fabrication of water splitting photoanodes with hole conductances near the maximum achievable with the given catalyst and Si substrate. Three methods for controlling the SiO2 interlayer thickness on the Si(100) surface for ALD-TiO2 protected anodes were employed: (1) TiO2 deposition directly on an HF-etched Si(100) surface, (2) TiO2 deposition after SiO2 atomic layer deposition on an HF-etched Si(100) surface, and (3) oxygen scavenging, post-TiO2 deposition to decompose the SiO2 layer using a Ti overlayer. Each of these methods provides a progressively superior means of reliably thinning the interfacial SiO2 layer, enabling the fabrication of efficient and stable water oxidation silicon anodes.

Design principles for maximizing photovoltage in metal-oxide-protected water-splitting photoanodes

Metal oxide protection layers for photoanodes may enable the development of large-scale solar fuel and solar chemical synthesis, but the poor photovoltages often reported so far will severely limit their performance. Here we report a novel observation of photovoltage loss associated with a charge extraction barrier imposed by the protection layer, and, by eliminating it, achieve photovoltages as high as 630mV, the maximum reported so far for water-splitting silicon photoanodes. The loss mechanism is systematically probed in metal-insulator-semiconductor Schottky junction cells compared to buried junction p(+) n cells, revealing the need to maintain a characteristic hole density at the semiconductor/insulator interface. A leaky-capacitor model related to the dielectric properties of the protective oxide explains this loss, achieving excellent agreement with the data. From these findings, we formulate design principles for simultaneous optimization of built-in field, interface quality, and hole extraction to maximize the photovoltage of oxide-protected water-splitting anodes.

Investigation of electrically active defects at the interface of high-k dielectrics and compound semiconductors

As silicon based devices in integrated circuits reach the fundamental limits of dimensional scaling there is growing research interest in the use of high electron mobility channel materials, such as indium gallium arsenide (InGaAs), in conjunction with high dielectric constant (high-k) gate oxides, for Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) based devices. The motivation for employing high mobility channel materials is to reduce power dissipation in integrated circuits while also providing improved performance. One of the primary challenges to date in the field of III-V semiconductors has been the observation of high levels of defect densities at the high-k/III-V interface, which prevents surface inversion of the semiconductor. The work presented in this PhD thesis details the characterization of MOS devices incorporating high-k dielectrics on III-V semiconductors. The analysis examines the effect of modifying the semiconductor bandgap in MOS structures incorporating InxGa1-xAs (x: 0, 0.15. 0.3, 0.53) layers, the optimization of device passivation procedures designed to reduce interface defect densities, and analysis of such electrically active interface defect states for the high-k/InGaAs system. Devices are characterized primarily through capacitance-voltage (CV) and conductance-voltage (GV) measurements of MOS structures both as a function of frequency and temperature. In particular, the density of electrically active interface states was reduced to the level which allowed the observation of true surface inversion behavior in the In0.53Ga0.47As MOS system. This was achieved by developing an optimized (NH4)2S passivation, minimized air exposure, and atomic layer deposition of an Al2O3 gate oxide. An extraction of activation energies allows discrimination of the mechanisms responsible for the inversion response. Finally a new approach is described to determine the minority carrier generation lifetime and the oxide capacitance in MOS structures. The method is demonstrated for an In0.53Ga0.47As system, but is generally applicable to any MOS structure exhibiting a minority carrier response in inversion.