Development of a triple stage heat transformer for the recycling of low temperature heat energy

Absorption heat transformers are thermodynamic systems which are capable of recycling industrial waste heat energy by increasing its temperature. Triple stage heat transformers (TAHTs) can increase the temperature of this waste heat by up to approximately 145˚C. The principle factors influencing the thermodynamic performance of a TAHT and general points of operating optima were identified using a multivariate statistical analysis, prior to using heat exchange network modelling techniques to dissect the design of the TAHT and systematically reassemble it in order to minimise internal exergy destruction within the unit. This enabled first and second law efficiency improvements of up to 18.8% and 31.5% respectively to be achieved compared to conventional TAHT designs. The economic feasibility of such a thermodynamically optimised cycle was investigated by applying it to an oil refinery in Ireland, demonstrating that in general the capital cost of a TAHT makes it difficult to achieve acceptable rates of return. Decreasing the TAHT's capital cost may be achieved by redesigning its individual pieces of equipment and reducing their size. The potential benefits of using a bubble column absorber were therefore investigated in this thesis. An experimental bubble column was constructed and used to track the collapse of steam bubbles being absorbed into a hotter lithium bromide salt solution. Extremely high mass transfer coefficients of approximately 0.0012m/s were observed, showing significant improvements over previously investigated absorbers. Two separate models were developed, namely a combined heat and mass transfer model describing the rate of collapse of the bubbles, and a stochastic model describing the hydrodynamic motion of the collapsing vapour bubbles taking into consideration random fluctuations observed in the experimental data. Both models showed good agreement with the collected data, and demonstrated that the difference between the solution's temperature and its boiling temperature is the primary factor influencing the absorber's performance.

Nanowires for 3d silicon interconnection – low temperature compliant nanowire-polymer film for z-axis interconnect

Semiconductor chip packaging has evolved from single chip packaging to 3D heterogeneous system integration using multichip stacking in a single module. One of the key challenges in 3D integration is the high density interconnects that need to be formed between the chips with through-silicon-vias (TSVs) and inter-chip interconnects. Anisotropic Conductive Film (ACF) technology is one of the low-temperature, fine-pitch interconnect method, which has been considered as a potential replacement for solder interconnects in line with continuous scaling of the interconnects in the IC industry. However, the conventional ACF materials are facing challenges to accommodate the reduced pad and pitch size due to the micro-size particles and the particle agglomeration issue. A new interconnect material - Nanowire Anisotropic Conductive Film (NW-ACF), composed of high density copper nanowires of ~ 200 nm diameter and 10-30 µm length that are vertically distributed in a polymeric template, is developed in this work to tackle the constrains of the conventional ACFs and serves as an inter-chip interconnect solution for potential three-dimensional (3D) applications.

A study of silicon and germanium junctionless transistors

Technology boosters, such as strain, HKMG and FinFET, have been introduced into semiconductor industry to extend Moore’s law beyond 130 nm technology nodes. New device structures and channel materials are highly demanded to keep performance enhancement when the device scales beyond 22 nm. In this work, the properties and feasibility of the proposed Junctionless transistor (JNT) have been evaluated for both Silicon and Germanium channels. The performance of Silicon JNTs with 22 nm gate length have been characterized at elevated temperature and stressed conditions. Furthermore, steep Subthreshold Slopes (SS) in JNT and IM devices are compared. It is observed that the floating body in JNT is relatively dynamic comparing with that in IM devices and proper design of the device structure may further reduce the VD for a sub- 60 mV/dec subthreshold slope. Diode configuration of the JNT has also been evaluated, which demonstrates the first diode without junctions. In order to extend JNT structure into the high mobility material Germanium (Ge), a full process has been develop for Ge JNT. Germanium-on-Insulator (GeOI) wafers were fabricated using Smart-Cut with low temperature direct wafer bonding method. Regarding the lithography and pattern transfer, a top-down process of sub-50-nm width Ge nanowires is developed in this chapter and Ge nanowires with 35 nm width and 50 nm depth are obtained. The oxidation behaviour of Ge by RTO has been investigated and high-k passivation scheme using thermally grown GeO2 has been developed. With all developed modules, JNT with Ge channels have been fabricated by the CMOScompatible top-down process. The transistors exhibit the lowest subthreshold slope to date for Ge JNT. The devices with a gate length of 3 μm exhibit a SS of 216 mV/dec with an ION/IOFF current ratio of 1.2×103 at VD = -1 V and DIBL of 87 mV/V.

Development of germanium/silicon integration for near infrared detection

Silicon (Si) is the base material for electronic technologies and is emerging as a very attractive platform for photonic integrated circuits (PICs). PICs allow optical systems to be made more compact with higher performance than discrete optical components. Applications for PICs are in the area of fibre-optic communication, biomedical devices, photovoltaics and imaging. Germanium (Ge), due to its suitable bandgap for telecommunications and its compatibility with Si technology is preferred over III-V compounds as an integrated on-chip detector at near infrared wavelengths. There are two main approaches for Ge/Si integration: through epitaxial growth and through direct wafer bonding. The lattice mismatch of ~4.2% between Ge and Si is the main problem of the former technique which leads to a high density of dislocations while the bond strength and conductivity of the interface are the main challenges of the latter. Both result in trap states which are expected to play a critical role. Understanding the physics of the interface is a key contribution of this thesis. This thesis investigates Ge/Si diodes using these two methods. The effects of interface traps on the static and dynamic performance of Ge/Si avalanche photodetectors have been modelled for the first time. The thesis outlines the original process development and characterization of mesa diodes which were fabricated by transferring a ~700 nm thick layer of p-type Ge onto n-type Si using direct wafer bonding and layer exfoliation. The effects of low temperature annealing on the device performance and on the conductivity of the interface have been investigated. It is shown that the diode ideality factor and the series resistance of the device are reduced after annealing. The carrier transport mechanism is shown to be dominated by generation–recombination before annealing and by direct tunnelling in forward bias and band-to-band tunnelling in reverse bias after annealing. The thesis presents a novel technique to realise photodetectors where one of the substrates is thinned by chemical mechanical polishing (CMP) after bonding the Si-Ge wafers. Based on this technique, Ge/Si detectors with remarkably high responsivities, in excess of 3.5 A/W at 1.55 μm at −2 V, under surface normal illumination have been measured. By performing electrical and optical measurements at various temperatures, the carrier transport through the hetero-interface is analysed by monitoring the Ge band bending from which a detailed band structure of the Ge/Si interface is proposed for the first time. The above unity responsivity of the detectors was explained by light induced potential barrier lowering at the interface. To our knowledge this is the first report of light-gated responsivity for vertically illuminated Ge/Si photodiodes. The wafer bonding approach followed by layer exfoliation or by CMP is a low temperature wafer scale process. In principle, the technique could be extended to other materials such as Ge on GaAs, or Ge on SOI. The unique results reported here are compatible with surface normal illumination and are capable of being integrated with CMOS electronics and readout units in the form of 2D arrays of detectors. One potential future application is a low-cost Si process-compatible near infrared camera.

Computational modeling of defects in nanoscale device materials

This PhD thesis concerns the computational modeling of the electronic and atomic structure of point defects in technologically relevant materials. Identifying the atomistic origin of defects observed in the electrical characteristics of electronic devices has been a long-term goal of first-principles methods. First principles simulations are performed in this thesis, consisting of density functional theory (DFT) supplemented with many body perturbation theory (MBPT) methods, of native defects in bulk and slab models of In0.53Ga0.47As. The latter consist of (100) - oriented surfaces passivated with A12O3. Our results indicate that the experimentally extracted midgap interface state density (Dit) peaks are not the result of defects directly at the semiconductor/oxide interface, but originate from defects in a more bulk-like chemical environment. This conclusion is reached by considering the energy of charge transition levels for defects at the interface as a function of distance from the oxide. Our work provides insight into the types of defects responsible for the observed departure from ideal electrical behaviour in III-V metal-oxidesemiconductor (MOS) capacitors. In addition, the formation energetics and electron scattering properties of point defects in carbon nanotubes (CNTs) are studied using DFT in conjunction with Green’s function based techniques. The latter are applied to evaluate the low-temperature, low-bias Landauer conductance spectrum from which mesoscopic transport properties such as the elastic mean free path and localization length of technologically relevant CNT sizes can be estimated from computationally tractable CNT models. Our calculations show that at CNT diameters pertinent to interconnect applications, the 555777 divacancy defect results in increased scattering and hence higher electrical resistance for electron transport near the Fermi level.