The morphology of ordered block copolymer patterns as probed by high resolution imaging

The microphase separation of block copolymer (BCP) thin films can afford a simple and cost-effective means to studying nanopattern surfaces, and especially the fabrication of nanocircuitry. However, because of complex interface effects and other complications, their 3D morphology, which is often critical for application, can be more complex than first thought. Here, we describe how emerging microscopic methods may be used to study complex BCP patterns and reveal their rich detail. These methods include helium ion microscopy (HIM) and high resolution x-section transmission electron microscopy (XTEM), and complement conventional secondary electron and atomic force microscopies (SEM and TEM). These techniques reveal that these structures are quite different to what might be expected. We illustrate the advances in the understanding of BCP thin film morphology in several systems, which result from this characterization. The systems described include symmetric, lamellar forming polystyrene-b-polymethylmethacrylate (PS-b-PMMA), cylinder forming polystyrene-b-polydimethylsiloxane (PS-b-PDMS), as well as lamellar and cylinder forming patterns of polystyrene-b-polyethylene oxide (PS-b-PEO) and polystyrene-b-poly-4-vinylpyridine (PS-b-P4VP). Each of these systems exhibits more complex arrangements than might be first thought. Finding and developing techniques whereby complex morphologies, particularly at very small dimensions, can be determined is critical to the practical use of these materials in many applications. The importance of quantifying these complex morphologies has implications for their use in integrated circuit manufacture, where they are being explored as alternative pattern forming methods to conventional UV lithography.

Photonic packaging: transforming silicon photonic integrated circuits into photonic devices

Dedicated multi-project wafer (MPW) runs for photonic integrated circuits (PICs) from Si foundries mean that researchers and small-to-medium enterprises (SMEs) can now afford to design and fabricate Si photonic chips. While these bare Si-PICs are adequate for testing new device and circuit designs on a probe-station, they cannot be developed into prototype devices, or tested outside of the laboratory, without first packaging them into a durable module. Photonic packaging of PICs is significantly more challenging, and currently orders of magnitude more expensive, than electronic packaging, because it calls for robust micron-level alignment of optical components, precise real-time temperature control, and often a high degree of vertical and horizontal electrical integration. Photonic packaging is perhaps the most significant bottleneck in the development of commercially relevant integrated photonic devices. This article describes how the key optical, electrical, and thermal requirements of Si-PIC packaging can be met, and what further progress is needed before industrial scale-up can be achieved.