Development of inversion-mode and junctionless Indium-Gallium-Arsenide MOSFETs

This PhD covers the development of planar inversion-mode and junctionless Al2O3/In0.53Ga0.47As metal-oxidesemiconductor field-effect transistors (MOSFETs). An implant activation anneal was developed for the formation of the source and drain (S/D) of the inversionmode MOSFET. Fabricated inversion-mode devices were used as test vehicles to investigate the impact of forming gas annealing (FGA) on device performance. Following FGA, the devices exhibited a subthreshold swing (SS) of 150mV/dec., an ION/IOFF of 104 and the transconductance, drive current and peak effective mobility increased by 29%, 25% and 15%, respectively. An alternative technique, based on the fitting of the measured full-gate capacitance vs gate voltage using a selfconsistent Poisson-Schrödinger solver, was developed to extract the trap energy profile across the full In0.53Ga0.47As bandgap and beyond. A multi-frequency inversion-charge pumping approach was proposed to (1) study the traps located at energy levels aligned with the In0.53Ga0.47As conduction band and (2) separate the trapped charge and mobile charge contributions. The analysis revealed an effective mobility (μeff) peaking at ~2850cm2/V.s for an inversion-charge density (Ninv) = 7*1011cm2 and rapidly decreasing to ~600cm2/V.s for Ninv = 1*1013 cm2, consistent with a μeff limited by surface roughness scattering. Atomic force microscopy measurements confirmed a large surface roughness of 1.95±0.28nm on the In0.53Ga0.47As channel caused by the S/D activation anneal. In order to circumvent the issue relative to S/D formation, a junctionless In0.53Ga0.47As device was developed. A digital etch was used to thin the In0.53Ga0.47As channel and investigate the impact of channel thickness (tInGaAs) on device performance. Scaling of the SS with tInGaAs was observed for tInGaAs going from 24 to 16nm, yielding a SS of 115mV/dec. for tInGaAs = 16nm. Flat-band μeff values of 2130 and 1975cm2/V.s were extracted on devices with tInGaAs of 24 and 20nm, respectively

Bottom-up growth of fully transparent contact layers of indium tin oxide nanowires for light-emitting devices

Thin layers of indium tin oxide are widely used as transparent coatings and electrodes in solar energy cells, flat-panel displays, antireflection coatings, radiation protection and lithium-ion battery materials, because they have the characteristics of low resistivity, strong absorption at ultraviolet wavelengths, high transmission in the visible, high reflectivity in the far-infrared and strong attenuation in the microwave region. However, there is often a trade-off between electrical conductivity and transparency at visible wavelengths for indium tin oxide and other transparent conducting oxides. Here, we report the growth of layers of indium tin oxide nanowires that show optimum electronic and photonic properties and demonstrate their use as fully transparent top contacts in the visible to near-infrared region for light-emitting devices.

Synthesis of indium nanoparticles at ambient temperature; simultaneous phase transfer and ripening

The synthesis of size-monodispersed indium nanoparticles via an innovative simultaneous phase transfer and ripening method is reported. The formation of nanoparticles occurs in a one-step process instead of well-known two-step phase transfer approaches. The synthesis involves the reduction of InCl3 with LiBH4 at ambient temperature and although the reduction occurs at room temperature, fine indium nanoparticles, with a mean diameter of 6.4 ± 0.4 nm, were obtained directly in non-polar n-dodecane. The direct synthesis of indium nanoparticles in n-dodecane facilitates their fast formation and enhances their size-monodispersity. In addition, the nanoparticles were highly stable for more than 2 months. The nanoparticles were characterised by dynamic light scattering (DLS), small angle X-ray scattering (SAXS), transmission electron microscopy (TEM), energy dispersive X-ray spectroscopy (EDS) and Fourier transform infrared (FT-IR) spectroscopy to determine their morphology, structure and phase purity.

Continuous non-destructive monitoring of cell health using impedance based interdigitated electrode structured sensors

This article examines some preliminary tests which were performed in order to evaluate the best electrode configuration (width and spacing) for cell culture analyses. Biochips packaged with indium tin oxide (ITO) interdigitated electrodes (IDEs) were used to perform impedance measurements on A549 cells cultured on the surface of the biochip. Several tests were carried out using a 10 mM solution of Sodium Chloride (NaCl), cell medium and the cell culture itself to characterize some of the configurations already fabricated in the facilities at Tyndall National Institute.

High-efficiency photovoltaics through mechanically stacked integration of solar cells based on the InP lattice constant

Solar Energy is a clean and abundant energy source that can help reduce reliance on fossil fuels around which questions still persist about their contribution to climate and long-term availability. Monolithic triple-junction solar cells are currently the state of the art photovoltaic devices with champion cell efficiencies exceeding 40%, but their ultimate efficiency is restricted by the current-matching constraint of series-connected cells. The objective of this thesis was to investigate the use of solar cells with lattice constants equal to InP in order to reduce the constraint of current matching in multi-junction solar cells. This was addressed by two approaches: Firstly, the formation of mechanically stacked solar cells (MSSC) was investigated through the addition of separate connections to individual cells that make up a multi-junction device. An electrical and optical modelling approach identified separately connected InGaAs bottom cells stacked under dual-junction GaAs based top cells as a route to high efficiency. An InGaAs solar cell was fabricated on an InP substrate with a measured 1-Sun conversion efficiency of 9.3%. A comparative study of adhesives found benzocyclobutene to be the most suitable for bonding component cells in a mechanically stacked configuration owing to its higher thermal conductivity and refractive index when compared to other candidate adhesives. A flip-chip process was developed to bond single-junction GaAs and InGaAs cells with a measured 4-terminal MSSC efficiency of 25.2% under 1-Sun conditions. Additionally, a novel InAlAs solar cell was identified, which can be used to provide an alternative to the well established GaAs solar cell. As wide bandgap InAlAs solar cells have not been extensively investigated for use in photovoltaics, single-junction cells were fabricated and their properties relevant to PV operation analysed. Minority carrier diffusion lengths in the micrometre range were extracted, confirming InAlAs as a suitable material for use in III-V solar cells, and a 1-Sun conversion efficiency of 6.6% measured for cells with 800 nm thick absorber layers. Given the cost and small diameter of commercially available InP wafers, InGaAs and InAlAs solar cells were fabricated on alternative substrates, namely GaAs. As a first demonstration the lattice constant of a GaAs substrate was graded to InP using an InxGa1-xAs metamorphic buffer layer onto which cells were grown. This was the first demonstration of an InAlAs solar cell on an alternative substrate and an initial step towards fabricating these cells on Si. The results presented offer a route to developing multi-junction solar cell devices based on the InP lattice parameter, thus extending the range of available bandgaps for high efficiency cells.

Atomic layer deposition of interface control layers for the fabrication of III/V MOS devices

The continued advancement of metal oxide semiconductor field effect transistor (MOSFET) technology has shifted the focus from Si/SiO2 transistors towards high-κ/III-V transistors for high performance, faster devices. This has been necessary due to the limitations associated with the scaling of the SiO2 thickness below ~1 nm and the associated increased leakage current due to direct electron tunnelling through the gate oxide. The use of these materials exhibiting lower effective charge carrier mass in conjunction with the use of a high-κ gate oxide allows for the continuation of device scaling and increases in the associated MOSFET device performance. The high-κ/III-V interface is a critical challenge to the integration of high-κ dielectrics on III-V channels. The interfacial chemistry of the high-κ/III-V system is more complex than Si, due to the nature of the multitude of potential native oxide chemistries at the surface with the resultant interfacial layer showing poor electrical insulating properties when high-κ dielectrics are deposited directly on these oxides. It is necessary to ensure that a good quality interface is formed in order to reduce leakage and interface state defect density to maximise channel mobility and reduce variability and power dissipation. In this work, the ALD growth of aluminium oxide (Al2O3) and hafnium oxide (HfO2) after various surface pre-treatments was carried out, with the aim of improving the high-κ/III-V interface by reducing the Dit – the density of interface defects caused by imperfections such as dangling bonds, dimers and other unsatisfied bonds at the interfaces of materials. A brief investigation was performed into the structural and electrical properties of Al2O3 films deposited on In0.53Ga0.47As at 200 and 300oC via a novel amidinate precursor. Samples were determined to experience a severe nucleation delay when deposited directly on native oxides, leading to diminished functionality as a gate insulator due to largely reduced growth per cycle. Aluminium oxide MOS capacitors were prepared by ALD and the electrical characteristics of GaAs, In0.53Ga0.47As and InP capacitors which had been exposed to pre-pulse treatments from triethyl gallium and trimethyl indium were examined, to determine if self-cleaning reactions similar to those of trimethyl aluminium occur for other alkyl precursors. An improved C-V characteristic was observed for GaAs devices indicating an improved interface possibly indicating an improvement of the surface upon pre-pulsing with TEG, conversely degraded electrical characteristics observed for In0.53Ga0.47As and InP MOS devices after pre-treatment with triethyl gallium and trimethyl indium respectively. The electrical characteristics of Al2O3/In0.53Ga0.47As MOS capacitors after in-situ H2/Ar plasma treatment or in-situ ammonium sulphide passivation were investigated and estimates of interface Dit calculated. The use of plasma reduced the amount of interface defects as evidenced in the improved C-V characteristics. Samples treated with ammonium sulphide in the ALD chamber were found to display no significant improvement of the high-κ/III-V interface. HfO2 MOS capacitors were fabricated using two different precursors comparing the industry standard hafnium chloride process with deposition from amide precursors incorporating a ~1nm interface control layer of aluminium oxide and the structural and electrical properties investigated. Capacitors furnished from the chloride process exhibited lower hysteresis and improved C-V characteristics as compared to that of hafnium dioxide grown from an amide precursor, an indication that no etching of the film takes place using the chloride precursor in conjunction with a 1nm interlayer. Optimisation of the amide process was carried out and scaled samples electrically characterised in order to determine if reduced bilayer structures display improved electrical characteristics. Samples were determined to exhibit good electrical characteristics with a low midgap Dit indicative of an unpinned Fermi level

The role of structure in the electrochemical performance of nanostructured metal oxides for lithium ion battery anodes

The Li-ion battery has for a number of years been a key factor that has enabled an ever increasing number of modern consumer devices, while in recent years has also been sought to power a range of emerging electric and hybrid electric vehicles. Due to their importance and popularity, a number of characteristics of Li-ion batteries have been subjected to intense work aimed at radical improvement. Although electrode material selection intrinsically defines characteristics like maximum capacity or voltage, engineering of the electrode structure may yield significant improvements to the lifetime performance of the battery, which would not be available if the material was used in its bulk form. The body of work presented in this thesis describes the relationship between the structure of electrochemically active materials and the course of the electrochemical processes occurring within the electrode. Chapter one describes the motivation behind the research presented herein. Chapter two serves to highlight a number of key advancements which have been made and detailed in the literature over recent years, pertaining to the use of nanostructured materials in Li-ion technology. Chapter three details methods and techniques applied in developing the body of work presented in this thesis. Chapter four details structural, molecular and electrochemical characteristics of tin oxide nanoparticle based electrodes, with particular emphasis on the relationship between the size distribution and the electrode performance. Chapter five presents findings of structural, electrochemical and optical study of indium oxide nanoparticles grown on silicon by molecular beam epitaxy. In chapter 6, tin oxide inverted opal electrodes are investigated for the conduct of the electrochemical performance of the electrodes under varying rate of change of potential. Chapter 7 presents the overall conclusions drawn from the results presented in this thesis, coupled with an indication of potential future work which may be explored further.

A highly efficient sensor platform using simply manufactured nanodot patterned substrates

Block copolymer (BCP) self-assembly is a low-cost means to nanopattern surfaces. Here, we use these nanopatterns to directly print arrays of nanodots onto a conducting substrate (Indium Tin Oxide (ITO) coated glass) for application as an electrochemical sensor for ethanol (EtOH) and hydrogen peroxide (H

An investigation by AFM and TEM of the mechanism of anodic formation of nanoporosity in n-InP in KOH

The early stages of nanoporous layer formation, under anodic conditions in the absence of light, were investigated for n-type InP with a carrier concentration of ∼3× 1018 cm-3 in 5 mol dm-3 KOH and a mechanism for the process is proposed. At potentials less than ∼0.35 V, spectroscopic ellipsometry and transmission electron microscopy (TEM) showed a thin oxide film on the surface. Atomic force microscopy (AFM) of electrode surfaces showed no pitting below ∼0.35 V but clearly showed etch pit formation in the range 0.4-0.53 V. The density of surface pits increased with time in both linear potential sweep and constant potential reaching a constant value at a time corresponding approximately to the current peak in linear sweep voltammograms and current-time curves at constant potential. TEM clearly showed individual nanoporous domains separated from the surface by a dense ∼40 nm InP layer. It is concluded that each domain develops as a result of directionally preferential pore propagation from an individual surface pit which forms a channel through this near-surface layer. As they grow larger, domains meet, and the merging of multiple domains eventually leads to a continuous nanoporous sub-surface region.

Anodic formation and characterization of nanoporous InP in aqueous KOH electrolytes

The anodic behavior of highly doped (> 1018 cm-3) n-InP in aqueous KOH was investigated. Electrodes anodized in the absence of light in 2- 5 mol dm-3 KOH at a constant potential of 0.5- 0.75 V (SCE), or subjected to linear potential sweeps to potentials in this range, were shown to exhibit the formation of a nanoporous subsurface region. Both linear sweep voltammograms and current-time curves at constant potential showed a characteristic anodic peak, corresponding to formation of the nanoporous region. No porous region was formed during anodization in 1 mol dm-3 KOH. The nanoporous region was examined using transmission electron microscopy and found to have a thickness of some 1- 3 μm depending on the anodization conditions and to be located beneath a thin (typically ∼40 nm), dense, near-surface layer. The pores varied in width from 25 to 75 nm and both the pore width and porous region thickness were found to decrease with increasing KOH concentration. The porosity was approximately 35%. The porous layer structure is shown to form by the localized penetration of surface pits into the InP, and the dense, near-surface layer is consistent with the effect of electron depletion at the surface of the semiconductor.

Simultaneous observation of current oscillations and porous film growth during anodization of InP

The observation of spontaneous oscillations in current during the anodization of InP in relatively high concentrations of KOH electrolytes is reported. Oscillations were observed under potential sweep and constant potential conditions. Well-defined oscillations are observed during linear potential sweeps of InP in 5 mol dm-3 KOH to potentials above ∼1.7 V (SCE) at scan rates in the range of 50 to 500 mV s-1. The oscillations observed exhibit an asymmetrical current versus potential profile, and the charge per cycle was found to increase linearly with potential. More complex oscillatory behavior was observed under constant potential conditions. Periodic damped oscillations are observed in high concentrations of electrolyte whereas undamped sinusoidal oscillations are observed in relatively lower concentrations. In both cases, the anodization of InP results in porous InP formation, and the current in the oscillatory region corresponds to the cyclical effective area changes due to pitting dissolution of the InP surface with the coincidental growth of a thick porous In2O3 film.

Investigation of electrically active defects at the interface of high-k dielectrics and compound semiconductors

As silicon based devices in integrated circuits reach the fundamental limits of dimensional scaling there is growing research interest in the use of high electron mobility channel materials, such as indium gallium arsenide (InGaAs), in conjunction with high dielectric constant (high-k) gate oxides, for Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) based devices. The motivation for employing high mobility channel materials is to reduce power dissipation in integrated circuits while also providing improved performance. One of the primary challenges to date in the field of III-V semiconductors has been the observation of high levels of defect densities at the high-k/III-V interface, which prevents surface inversion of the semiconductor. The work presented in this PhD thesis details the characterization of MOS devices incorporating high-k dielectrics on III-V semiconductors. The analysis examines the effect of modifying the semiconductor bandgap in MOS structures incorporating InxGa1-xAs (x: 0, 0.15. 0.3, 0.53) layers, the optimization of device passivation procedures designed to reduce interface defect densities, and analysis of such electrically active interface defect states for the high-k/InGaAs system. Devices are characterized primarily through capacitance-voltage (CV) and conductance-voltage (GV) measurements of MOS structures both as a function of frequency and temperature. In particular, the density of electrically active interface states was reduced to the level which allowed the observation of true surface inversion behavior in the In0.53Ga0.47As MOS system. This was achieved by developing an optimized (NH4)2S passivation, minimized air exposure, and atomic layer deposition of an Al2O3 gate oxide. An extraction of activation energies allows discrimination of the mechanisms responsible for the inversion response. Finally a new approach is described to determine the minority carrier generation lifetime and the oxide capacitance in MOS structures. The method is demonstrated for an In0.53Ga0.47As system, but is generally applicable to any MOS structure exhibiting a minority carrier response in inversion.

MOVPE growth and characterization of Al(Ga)N and InAlN/AlGaN quantum wells for UV LED applications

The study of III-nitride materials (InN, GaN and AlN) gained huge research momentum after breakthroughs in the production light emitting diodes (LEDs) and laser diodes (LDs) over the past two decades. Last year, the Nobel Prize in Physics was awarded jointly to Isamu Akasaki, Hiroshi Amano and Shuji Nakamura for inventing a new energy efficient and environmental friendly light source: blue light-emitting diode (LED) from III-nitride semiconductors in the early 1990s. Nowadays, III-nitride materials not only play an increasingly important role in the lighting technology, but also become prospective candidates in other areas, for example, the high frequency (RF) high electron mobility transistor (HEMT) and photovoltaics. These devices require the growth of high quality III-nitride films, which can be prepared using metal organic vapour phase epitaxy (MOVPE). The main aim of my thesis is to study and develop the growth of III-nitride films, including AlN, u-AlGaN, Si-doped AlGaN, and InAlN, serving as sample wafers for fabrication of ultraviolet (UV) LEDs, in order to replace the conventional bulky, expensive and environmentally harmful mercury lamp as new UV light sources. For application to UV LEDs, reducing the threading dislocation density (TDD) in AlN epilayers on sapphire substrates is a key parameter for achieving high-efficiency AlGaNbased UV emitters. In Chapter 4, after careful and systematic optimisation， a working set of conditions, the screw and edge type dislocation density in the AlN were reduced to around 2.2×108 cm-2 and 1.3×109 cm-2 , respectively, using an optimized three-step process, as estimated by TEM. An atomically smooth surface with an RMS roughness of around 0.3 nm achieved over 5×5 µm 2 AFM scale. Furthermore, the motion of the steps in a one dimension model has been proposed to describe surface morphology evolution, especially the step bunching feature found under non-optimal conditions. In Chapter 5, control of alloy composition and the maintenance of compositional uniformity across a growing epilayer surface were demonstrated for the development of u-AlGaN epilayers. Optimized conditions (i.e. a high growth temperature of 1245 °C) produced uniform and smooth film with a low RMS roughness of around 2 nm achieved in 20×20 µm 2 AFM scan. The dopant that is most commonly used to obtain n-type conductivity in AlxGa1-xN is Si. However, the incorporation of Si has been found to increase the strain relaxation and promote unintentional incorporation of other impurities (O and C) during Si-doped AlGaN growth. In Chapter 6, reducing edge-type TDs is observed to be an effective appoach to improve the electric and optical properties of Si-doped AlGaN epilayers. In addition, the maximum electron concentration of 1.3×1019 cm-3 and 6.4×1018 cm-3 were achieved in Si-doped Al0.48Ga0.52N and Al0.6Ga0.4N epilayers as measured using Hall effect. Finally, in Chapter 7, studies on the growth of InAlN/AlGaN multiple quantum well (MQW) structures were performed, and exposing InAlN QW to a higher temperature during the ramp to the growth temperature of AlGaN barrier (around 1100 °C) will suffer a significant indium (In) desorption. To overcome this issue, quasi-two-tempeature (Q2T) technique was applied to protect InAlN QW. After optimization, an intense UV emission from MQWs has been observed in the UV spectral range from 320 to 350 nm measured by room temperature photoluminescence.

Heterogeneously grown tunable group-IV laser on silicon

Tunable tensile-strained germanium (epsilon-Ge) thin films on GaAs and heterogeneously integrated on silicon (Si) have been demonstrated using graded III-V buffer architectures grown by molecular beam epitaxy (MBE). epsilon-Ge epilayers with tunable strain from 0% to 1.95% on GaAs and 0% to 1.11% on Si were realized utilizing MBE. The detailed structural, morphological, band alignment and optical properties of these highly tensile-strained Ge materials were characterized to establish a pathway for wavelength-tunable laser emission from 1.55 μm to 2.1 μm. High-resolution X-ray analysis confirmed pseudomorphic epsilon-Ge epitaxy in which the amount of strain varied linearly as a function of indium alloy composition in the InxGa1-xAs buffer. Cross-sectional transmission electron microscopic analysis demonstrated a sharp heterointerface between the epsilon-Ge and the InxGa1-xAs layer and confirmed the strain state of the epsilon-Ge epilayer. Lowtemperature micro-photoluminescence measurements confirmed both direct and indirect bandgap radiative recombination between the Γ and L valleys of Ge to the light-hole valence band, with L-lh bandgaps of 0.68 eV and 0.65 eV demonstrated for the 0.82% and 1.11% epsilon-Ge on Si, respectively. The highly epsilon-Ge exhibited a direct bandgap, and wavelength-tunable emission was observed for all samples on both GaAs and Si. Successful heterogeneous integration of tunable epsilon-Ge quantum wells on Si paves the way for the implementation of monolithic heterogeneous devices on Si.

Theory and optimisation of 1.3 and 1.55 μm (Al)InGaAs metamorphic quantum well lasers

The use of InGaAs metamorphic buffer layers (MBLs) to facilitate the growth of lattice-mismatched heterostructures constitutes an attractive approach to developing long-wavelength semiconductor lasers on GaAs substrates, since they offer the improved carrier and optical confinement associated with GaAs-based materials. We present a theoretical study of GaAs-based 1.3 and 1.55 μm (Al)InGaAs quantum well (QW) lasers grown on InGaAs MBLs. We demonstrate that optimised 1.3 μm metamorphic devices offer low threshold current densities and high differential gain, which compare favourably with InP-based devices. Overall, our analysis highlights and quantifies the potential of metamorphic QWs for the development of GaAs-based long-wavelength semiconductor lasers, and also provides guidelines for the design of optimised devices.