All-optical modulation converter for on-off keying to duobinary and alternate-mark inversion at 42.6 Gbps

Advanced modulation formats have become increasingly important as telecoms engineers strive for improved tolerance to both linear and nonlinear fibre-based transmission impairments. Two important modulation schemes are Duobinary (DB) and Alternate-mark inversion (AMI) [1] where transmission enhancement results from auxiliary phase modulation. As advanced modulation formats displace Return-to-zero On-Off Keying (RZ-OOK), inter-modulation converters will become increasingly important. If the modulation conversion can be performed at high bitrates with a small number of operations per bit, then all-optical techniques may offer lower energy consumption compared to optical-electronic-optical approaches. In this paper we experimentally demonstrate an all-optical system incorporating a pair of hybrid-integrated semiconductor optical amplifier (SOA)-based Mach-Zehnder interferometer (MZI) gates which translate RZ-OOK to RZ-DB or RZ-AMI at 42.6 Gbps. This scheme includes a wavelength conversion to arbitrary output wavelength and has potential for high-level photonic integration, scalability to higher bitrates, and should exhibit regenerative properties [2].

Novel all-optical on-off-keyed to alternate-mark-inversion converter

We numerically investigate a novel 40 Gbps OOK to AMI all-optical modulation format converter employing an SOA-based Mach-Zehnder interferometer.  We demonstrate operation with a 27-1 PRBS and explain the phase modulation's relationship with patterning.

Design and implementation of the embedded capacitance layers for decoupling of wireless sensor nodes

In this paper, the embedded capacitance material (ECM) is fabricated between the power and ground layers of the wireless sensor nodes, forming an integrated capacitance to replace the large amount of decoupling capacitors on the board. The ECM material, whose dielectric constant is 16, has the same size of the wireless sensor nodes of 3cm*3cm, with a thickness of only 14μm. Though the capacitance of a single ECM layer being only around 8nF, there are two reasons the ECM layers can still replace the high frequency decoupling capacitors (100nF in our case) on the board. The first reason is: the parasitic inductance of the ECM layer is much lower than the surface mount capacitors'. A smaller capacitance value of the ECM layer could achieve the same resonant frequency of the surface mount decoupling capacitors. Simulation and measurement fit this assumption well. The second reason is: more than one layer of ECM material are utilized during the design step to get a parallel connection of the several ECM capacitance layers, finally leading to a larger value of the capacitance and smaller value of parasitic. Characterization of the ECM is carried out by the LCR meter. To evaluate the behaviors of the ECM layer, time and frequency domain measurements are performed on the power-bus decoupling of the wireless sensor nodes. Comparison with the measurements of bare PCB board and decoupling capacitors solution are provided to show the improvement of the ECM layer. Measurements show that the implementation of the ECM layer can not only save the space of the surface mount decoupling capacitors, but also provide better power-bus decoupling to the nodes.

Advanced polymer membrane development in pervaporation dehydration and lateral flow diagnostics

The work in this thesis concerns the advanced development of polymeric membranes of two types; pervaporation and lateral-flow. The former produced from a solution casting method and the latter from a phase separation. All membranes were produced from casting lacquers. Early research centred on the development of viable membranes. This led to a supported polymer blend pervaporation membrane. Selective layer: plasticized 4:1 mass ratio sodium-alginate: poly(vinyl-alcohol) polymer blend. Using this membrane, pervaporation separation of ethanol/water mixtures was carefully monitored as a function of film thickness and time. Contrary to literature expectations, these films showed increased selectivity and decreased flux as film thickness was reduced. It is argued that morphology and structure of the polymer blend changes with thickness and that these changes define membrane efficiency. Mixed matrix membrane development was done using spherical, discreet, size-monodisperse mesoporous silica particles of 1.8 - 2μm diameter, with pore diameters of ~1.8 nm were incorporated into a poly(vinyl alcohol) [PVA] matrix. Inclusion of silica benefitted pervaporation performance for the dehydration of ethanol, improving flux and selectivity throughout in all but the highest silica content samples. Early lateral-flow membrane research produced a membrane from a basic lacquer composition required for phase inversion; polymer, solvent and non-solvent. Results showed that bringing lacquers to cloud point benefits both the pore structure and skin layers of the membranes. Advancement of this work showed that incorporation of ethanol as a mesosolvent into the lacquer effectively enhances membrane pore structure resulting in an improvement in lateral flow rates of the final membranes. This project details the formation mechanics of pervaporation and lateral-flow membranes and how these can be controlled. The principle methods of control can be applied to the formation of any other flat sheet polymer membranes, opening many avenues of future membrane research and industrial application.

Development of inversion-mode and junctionless Indium-Gallium-Arsenide MOSFETs

This PhD covers the development of planar inversion-mode and junctionless Al2O3/In0.53Ga0.47As metal-oxidesemiconductor field-effect transistors (MOSFETs). An implant activation anneal was developed for the formation of the source and drain (S/D) of the inversionmode MOSFET. Fabricated inversion-mode devices were used as test vehicles to investigate the impact of forming gas annealing (FGA) on device performance. Following FGA, the devices exhibited a subthreshold swing (SS) of 150mV/dec., an ION/IOFF of 104 and the transconductance, drive current and peak effective mobility increased by 29%, 25% and 15%, respectively. An alternative technique, based on the fitting of the measured full-gate capacitance vs gate voltage using a selfconsistent Poisson-Schrödinger solver, was developed to extract the trap energy profile across the full In0.53Ga0.47As bandgap and beyond. A multi-frequency inversion-charge pumping approach was proposed to (1) study the traps located at energy levels aligned with the In0.53Ga0.47As conduction band and (2) separate the trapped charge and mobile charge contributions. The analysis revealed an effective mobility (μeff) peaking at ~2850cm2/V.s for an inversion-charge density (Ninv) = 7*1011cm2 and rapidly decreasing to ~600cm2/V.s for Ninv = 1*1013 cm2, consistent with a μeff limited by surface roughness scattering. Atomic force microscopy measurements confirmed a large surface roughness of 1.95±0.28nm on the In0.53Ga0.47As channel caused by the S/D activation anneal. In order to circumvent the issue relative to S/D formation, a junctionless In0.53Ga0.47As device was developed. A digital etch was used to thin the In0.53Ga0.47As channel and investigate the impact of channel thickness (tInGaAs) on device performance. Scaling of the SS with tInGaAs was observed for tInGaAs going from 24 to 16nm, yielding a SS of 115mV/dec. for tInGaAs = 16nm. Flat-band μeff values of 2130 and 1975cm2/V.s were extracted on devices with tInGaAs of 24 and 20nm, respectively

Atomic layer deposition of interface control layers for the fabrication of III/V MOS devices

The continued advancement of metal oxide semiconductor field effect transistor (MOSFET) technology has shifted the focus from Si/SiO2 transistors towards high-κ/III-V transistors for high performance, faster devices. This has been necessary due to the limitations associated with the scaling of the SiO2 thickness below ~1 nm and the associated increased leakage current due to direct electron tunnelling through the gate oxide. The use of these materials exhibiting lower effective charge carrier mass in conjunction with the use of a high-κ gate oxide allows for the continuation of device scaling and increases in the associated MOSFET device performance. The high-κ/III-V interface is a critical challenge to the integration of high-κ dielectrics on III-V channels. The interfacial chemistry of the high-κ/III-V system is more complex than Si, due to the nature of the multitude of potential native oxide chemistries at the surface with the resultant interfacial layer showing poor electrical insulating properties when high-κ dielectrics are deposited directly on these oxides. It is necessary to ensure that a good quality interface is formed in order to reduce leakage and interface state defect density to maximise channel mobility and reduce variability and power dissipation. In this work, the ALD growth of aluminium oxide (Al2O3) and hafnium oxide (HfO2) after various surface pre-treatments was carried out, with the aim of improving the high-κ/III-V interface by reducing the Dit – the density of interface defects caused by imperfections such as dangling bonds, dimers and other unsatisfied bonds at the interfaces of materials. A brief investigation was performed into the structural and electrical properties of Al2O3 films deposited on In0.53Ga0.47As at 200 and 300oC via a novel amidinate precursor. Samples were determined to experience a severe nucleation delay when deposited directly on native oxides, leading to diminished functionality as a gate insulator due to largely reduced growth per cycle. Aluminium oxide MOS capacitors were prepared by ALD and the electrical characteristics of GaAs, In0.53Ga0.47As and InP capacitors which had been exposed to pre-pulse treatments from triethyl gallium and trimethyl indium were examined, to determine if self-cleaning reactions similar to those of trimethyl aluminium occur for other alkyl precursors. An improved C-V characteristic was observed for GaAs devices indicating an improved interface possibly indicating an improvement of the surface upon pre-pulsing with TEG, conversely degraded electrical characteristics observed for In0.53Ga0.47As and InP MOS devices after pre-treatment with triethyl gallium and trimethyl indium respectively. The electrical characteristics of Al2O3/In0.53Ga0.47As MOS capacitors after in-situ H2/Ar plasma treatment or in-situ ammonium sulphide passivation were investigated and estimates of interface Dit calculated. The use of plasma reduced the amount of interface defects as evidenced in the improved C-V characteristics. Samples treated with ammonium sulphide in the ALD chamber were found to display no significant improvement of the high-κ/III-V interface. HfO2 MOS capacitors were fabricated using two different precursors comparing the industry standard hafnium chloride process with deposition from amide precursors incorporating a ~1nm interface control layer of aluminium oxide and the structural and electrical properties investigated. Capacitors furnished from the chloride process exhibited lower hysteresis and improved C-V characteristics as compared to that of hafnium dioxide grown from an amide precursor, an indication that no etching of the film takes place using the chloride precursor in conjunction with a 1nm interlayer. Optimisation of the amide process was carried out and scaled samples electrically characterised in order to determine if reduced bilayer structures display improved electrical characteristics. Samples were determined to exhibit good electrical characteristics with a low midgap Dit indicative of an unpinned Fermi level