An investigation by AFM and TEM of the mechanism of anodic formation of nanoporosity in n-InP in KOH

The early stages of nanoporous layer formation, under anodic conditions in the absence of light, were investigated for n-type InP with a carrier concentration of ∼3× 1018 cm-3 in 5 mol dm-3 KOH and a mechanism for the process is proposed. At potentials less than ∼0.35 V, spectroscopic ellipsometry and transmission electron microscopy (TEM) showed a thin oxide film on the surface. Atomic force microscopy (AFM) of electrode surfaces showed no pitting below ∼0.35 V but clearly showed etch pit formation in the range 0.4-0.53 V. The density of surface pits increased with time in both linear potential sweep and constant potential reaching a constant value at a time corresponding approximately to the current peak in linear sweep voltammograms and current-time curves at constant potential. TEM clearly showed individual nanoporous domains separated from the surface by a dense ∼40 nm InP layer. It is concluded that each domain develops as a result of directionally preferential pore propagation from an individual surface pit which forms a channel through this near-surface layer. As they grow larger, domains meet, and the merging of multiple domains eventually leads to a continuous nanoporous sub-surface region.

Anodic formation and characterization of nanoporous InP in aqueous KOH electrolytes

The anodic behavior of highly doped (> 1018 cm-3) n-InP in aqueous KOH was investigated. Electrodes anodized in the absence of light in 2- 5 mol dm-3 KOH at a constant potential of 0.5- 0.75 V (SCE), or subjected to linear potential sweeps to potentials in this range, were shown to exhibit the formation of a nanoporous subsurface region. Both linear sweep voltammograms and current-time curves at constant potential showed a characteristic anodic peak, corresponding to formation of the nanoporous region. No porous region was formed during anodization in 1 mol dm-3 KOH. The nanoporous region was examined using transmission electron microscopy and found to have a thickness of some 1- 3 μm depending on the anodization conditions and to be located beneath a thin (typically ∼40 nm), dense, near-surface layer. The pores varied in width from 25 to 75 nm and both the pore width and porous region thickness were found to decrease with increasing KOH concentration. The porosity was approximately 35%. The porous layer structure is shown to form by the localized penetration of surface pits into the InP, and the dense, near-surface layer is consistent with the effect of electron depletion at the surface of the semiconductor.

Investigation of electrically active defects at the interface of high-k dielectrics and compound semiconductors

As silicon based devices in integrated circuits reach the fundamental limits of dimensional scaling there is growing research interest in the use of high electron mobility channel materials, such as indium gallium arsenide (InGaAs), in conjunction with high dielectric constant (high-k) gate oxides, for Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) based devices. The motivation for employing high mobility channel materials is to reduce power dissipation in integrated circuits while also providing improved performance. One of the primary challenges to date in the field of III-V semiconductors has been the observation of high levels of defect densities at the high-k/III-V interface, which prevents surface inversion of the semiconductor. The work presented in this PhD thesis details the characterization of MOS devices incorporating high-k dielectrics on III-V semiconductors. The analysis examines the effect of modifying the semiconductor bandgap in MOS structures incorporating InxGa1-xAs (x: 0, 0.15. 0.3, 0.53) layers, the optimization of device passivation procedures designed to reduce interface defect densities, and analysis of such electrically active interface defect states for the high-k/InGaAs system. Devices are characterized primarily through capacitance-voltage (CV) and conductance-voltage (GV) measurements of MOS structures both as a function of frequency and temperature. In particular, the density of electrically active interface states was reduced to the level which allowed the observation of true surface inversion behavior in the In0.53Ga0.47As MOS system. This was achieved by developing an optimized (NH4)2S passivation, minimized air exposure, and atomic layer deposition of an Al2O3 gate oxide. An extraction of activation energies allows discrimination of the mechanisms responsible for the inversion response. Finally a new approach is described to determine the minority carrier generation lifetime and the oxide capacitance in MOS structures. The method is demonstrated for an In0.53Ga0.47As system, but is generally applicable to any MOS structure exhibiting a minority carrier response in inversion.

Chemical approaches for doping nanodevice architectures

Advanced doping technologies are key for the continued scaling of semiconductor devices and the maintenance of device performance beyond the 14 nm technology node. Due to limitations of conventional ion-beam implantation with thin body and 3D device geometries, techniques which allow precise control over dopant diffusion and concentration, in addition to excellent conformality on 3D device surfaces, are required. Spin-on doping has shown promise as a conventional technique for doping new materials, particularly through application with other dopant methods, but may not be suitable for conformal doping of nanostructures. Additionally, residues remain after most spin-on-doping processes which are often difficult to remove. In-situ doping of nanostructures is especially common for bottom-up grown nanostructures but problems associated with concentration gradients and morphology changes are commonly experienced. Monolayer doping (MLD) has been shown to satisfy the requirements for extended defect-free, conformal and controllable doping on many materials ranging from traditional silicon and germanium devices to emerging replacement materials such as III-V compounds but challenges still remain, especially with regard to metrology and surface chemistry at such small feature sizes. This article summarises and critically assesses developments over the last number of years regarding the application of gas and solution phase techniques to dope silicon-, germanium- and III-V-based materials and nanostructures to obtain shallow diffusion depths coupled with high carrier concentrations and abrupt junctions.

Organic functionalisation, doping and characterisation of semiconductor surfaces for future CMOS device applications

Organic Functionalisation, Doping and Characterisation of Semiconductor Surfaces for Future CMOS Device Applications Semiconductor materials have long been the driving force for the advancement of technology since their inception in the mid-20th century. Traditionally, micro-electronic devices based upon these materials have scaled down in size and doubled in transistor density in accordance with the well-known Moore’s law, enabling consumer products with outstanding computational power at lower costs and with smaller footprints. According to the International Technology Roadmap for Semiconductors (ITRS), the scaling of metal-oxide-semiconductor field-effect transistors (MOSFETs) is proceeding at a rapid pace and will reach sub-10 nm dimensions in the coming years. This scaling presents many challenges, not only in terms of metrology but also in terms of the material preparation especially with respect to doping, leading to the moniker “More-than-Moore”. Current transistor technologies are based on the use of semiconductor junctions formed by the introduction of dopant atoms into the material using various methodologies and at device sizes below 10 nm, high concentration gradients become a necessity. Doping, the controlled and purposeful addition of impurities to a semiconductor, is one of the most important steps in the material preparation with uniform and confined doping to form ultra-shallow junctions at source and drain extension regions being one of the key enablers for the continued scaling of devices. Monolayer doping has shown promise to satisfy the need to conformally dope at such small feature sizes. Monolayer doping (MLD) has been shown to satisfy the requirements for extended defect-free, conformal and controllable doping on many materials ranging from the traditional silicon and germanium devices to emerging replacement materials such as III-V compounds This thesis aims to investigate the potential of monolayer doping to complement or replace conventional doping technologies currently in use in CMOS fabrication facilities across the world.

Heterogeneously grown tunable group-IV laser on silicon

Tunable tensile-strained germanium (epsilon-Ge) thin films on GaAs and heterogeneously integrated on silicon (Si) have been demonstrated using graded III-V buffer architectures grown by molecular beam epitaxy (MBE). epsilon-Ge epilayers with tunable strain from 0% to 1.95% on GaAs and 0% to 1.11% on Si were realized utilizing MBE. The detailed structural, morphological, band alignment and optical properties of these highly tensile-strained Ge materials were characterized to establish a pathway for wavelength-tunable laser emission from 1.55 μm to 2.1 μm. High-resolution X-ray analysis confirmed pseudomorphic epsilon-Ge epitaxy in which the amount of strain varied linearly as a function of indium alloy composition in the InxGa1-xAs buffer. Cross-sectional transmission electron microscopic analysis demonstrated a sharp heterointerface between the epsilon-Ge and the InxGa1-xAs layer and confirmed the strain state of the epsilon-Ge epilayer. Lowtemperature micro-photoluminescence measurements confirmed both direct and indirect bandgap radiative recombination between the Γ and L valleys of Ge to the light-hole valence band, with L-lh bandgaps of 0.68 eV and 0.65 eV demonstrated for the 0.82% and 1.11% epsilon-Ge on Si, respectively. The highly epsilon-Ge exhibited a direct bandgap, and wavelength-tunable emission was observed for all samples on both GaAs and Si. Successful heterogeneous integration of tunable epsilon-Ge quantum wells on Si paves the way for the implementation of monolithic heterogeneous devices on Si.

Role of substrate quality on the performance of semipolar (11 2 - 2) InGaN light-emitting diodes

We compare the optical properties and device performance of unpackaged InGaN/GaN multiple-quantum-well light-emitting diodes (LEDs) emitting at ∼430 nm grown simultaneously on a high-cost small-size bulk semipolar (11 2 - 2) GaN substrate (Bulk-GaN) and a low-cost large-size (11 2 - 2) GaN template created on patterned (10 1 - 2) r-plane sapphire substrate (PSS-GaN). The Bulk-GaN substrate has the threading dislocation density (TDD) of ∼ and basal-plane stacking fault (BSF) density of 0 cm-1, while the PSS-GaN substrate has the TDD of ∼2 × 108cm-2 and BSF density of ∼1 × 103cm-1. Despite an enhanced light extraction efficiency, the LED grown on PSS-GaN has two-times lower internal quantum efficiency than the LED grown on Bulk-GaN as determined by photoluminescence measurements. The LED grown on PSS-GaN substrate also has about two-times lower output power compared to the LED grown on Bulk-GaN substrate. This lower output power was attributed to the higher TDD and BSF density.