A study of silicon and germanium junctionless transistors

Technology boosters, such as strain, HKMG and FinFET, have been introduced into semiconductor industry to extend Moore’s law beyond 130 nm technology nodes. New device structures and channel materials are highly demanded to keep performance enhancement when the device scales beyond 22 nm. In this work, the properties and feasibility of the proposed Junctionless transistor (JNT) have been evaluated for both Silicon and Germanium channels. The performance of Silicon JNTs with 22 nm gate length have been characterized at elevated temperature and stressed conditions. Furthermore, steep Subthreshold Slopes (SS) in JNT and IM devices are compared. It is observed that the floating body in JNT is relatively dynamic comparing with that in IM devices and proper design of the device structure may further reduce the VD for a sub- 60 mV/dec subthreshold slope. Diode configuration of the JNT has also been evaluated, which demonstrates the first diode without junctions. In order to extend JNT structure into the high mobility material Germanium (Ge), a full process has been develop for Ge JNT. Germanium-on-Insulator (GeOI) wafers were fabricated using Smart-Cut with low temperature direct wafer bonding method. Regarding the lithography and pattern transfer, a top-down process of sub-50-nm width Ge nanowires is developed in this chapter and Ge nanowires with 35 nm width and 50 nm depth are obtained. The oxidation behaviour of Ge by RTO has been investigated and high-k passivation scheme using thermally grown GeO2 has been developed. With all developed modules, JNT with Ge channels have been fabricated by the CMOScompatible top-down process. The transistors exhibit the lowest subthreshold slope to date for Ge JNT. The devices with a gate length of 3 μm exhibit a SS of 216 mV/dec with an ION/IOFF current ratio of 1.2×103 at VD = -1 V and DIBL of 87 mV/V.

High speed nonlinear optical components for next-generation optical communications

Electronic signal processing systems currently employed at core internet routers require huge amounts of power to operate and they may be unable to continue to satisfy consumer demand for more bandwidth without an inordinate increase in cost, size and/or energy consumption. Optical signal processing techniques may be deployed in next-generation optical networks for simple tasks such as wavelength conversion, demultiplexing and format conversion at high speed (≥100Gb.s-1) to alleviate the pressure on existing core router infrastructure. To implement optical signal processing functionalities, it is necessary to exploit the nonlinear optical properties of suitable materials such as III-V semiconductor compounds, silicon, periodically-poled lithium niobate (PPLN), highly nonlinear fibre (HNLF) or chalcogenide glasses. However, nonlinear optical (NLO) components such as semiconductor optical amplifiers (SOAs), electroabsorption modulators (EAMs) and silicon nanowires are the most promising candidates as all-optical switching elements vis-à-vis ease of integration, device footprint and energy consumption. This PhD thesis presents the amplitude and phase dynamics in a range of device configurations containing SOAs, EAMs and/or silicon nanowires to support the design of all optical switching elements for deployment in next-generation optical networks. Time-resolved pump-probe spectroscopy using pulses with a pulse width of 3ps from mode-locked laser sources was utilized to accurately measure the carrier dynamics in the device(s) under test. The research work into four main topics: (a) a long SOA, (b) the concatenated SOA-EAMSOA (CSES) configuration, (c) silicon nanowires embedded in SU8 polymer and (d) a custom epitaxy design EAM with fast carrier sweepout dynamics. The principal aim was to identify the optimum operation conditions for each of these NLO device configurations to enhance their switching capability and to assess their potential for various optical signal processing functionalities. All of the NLO device configurations investigated in this thesis are compact and suitable for monolithic and/or hybrid integration.

Solid-state synthesis of embedded single-crystal metal oxide and phosphate nanoparticles and in situ crystallization

A new solid state organometallic route to embedded nanoparticle-containing inorganic materials is shown, through pyrolysis of metal-containing derivatives of cyclotriphosphazenes. Pyrolysis in air and at 800 °C of new molecular precursors gives individual single-crystal nanoparticles of SiP2O7, TiO2, P4O7, WP2O7 and SiO2, depending on the precursor used. High resolution transmission electron microscopy investigations reveal, in most cases, perfect single crystals of metal oxides and the first nanostructures of negative thermal expansion metal phosphates with diameters in the range 2–6 nm for all products. While all nanoparticles are new by this method, WP2O7 and SiP2O7 nanoparticles are reported for the first time. In situ recrystallization formation of nanocrystals of SiP2O7 was also observed due to electron beam induced reactions during measurements of the nanoparticulate pyrolytic products SiO2 and P4O7. The possible mechanism for the formation of the nanoparticles at much lower temperatures than their bulk counterparts in both cases is discussed. Degrees of stabilization from the formation of P4O7 affects the nanocrystalline products: nanoparticles are observed for WP2O7, with coalescing crystallization occurring for the amorphous host in which SiP2O7 crystals form as a solid within a solid. The approach allows the simple formation of multimetallic, monometallic, metal-oxide and metal phosphate nanocrystals embedded in an amorphous dielectric. The method and can be extended to nearly any metal capable of successful coordination as an organometallic to allow embedded nanoparticle layers and features to be deposited or written on surfaces for application as high mobility pyrophosphate lithium–ion cathode materials, catalysis and nanocrystal embedded dielectric layers.

Investigation of electrically active defects at the interface of high-k dielectrics and compound semiconductors

As silicon based devices in integrated circuits reach the fundamental limits of dimensional scaling there is growing research interest in the use of high electron mobility channel materials, such as indium gallium arsenide (InGaAs), in conjunction with high dielectric constant (high-k) gate oxides, for Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) based devices. The motivation for employing high mobility channel materials is to reduce power dissipation in integrated circuits while also providing improved performance. One of the primary challenges to date in the field of III-V semiconductors has been the observation of high levels of defect densities at the high-k/III-V interface, which prevents surface inversion of the semiconductor. The work presented in this PhD thesis details the characterization of MOS devices incorporating high-k dielectrics on III-V semiconductors. The analysis examines the effect of modifying the semiconductor bandgap in MOS structures incorporating InxGa1-xAs (x: 0, 0.15. 0.3, 0.53) layers, the optimization of device passivation procedures designed to reduce interface defect densities, and analysis of such electrically active interface defect states for the high-k/InGaAs system. Devices are characterized primarily through capacitance-voltage (CV) and conductance-voltage (GV) measurements of MOS structures both as a function of frequency and temperature. In particular, the density of electrically active interface states was reduced to the level which allowed the observation of true surface inversion behavior in the In0.53Ga0.47As MOS system. This was achieved by developing an optimized (NH4)2S passivation, minimized air exposure, and atomic layer deposition of an Al2O3 gate oxide. An extraction of activation energies allows discrimination of the mechanisms responsible for the inversion response. Finally a new approach is described to determine the minority carrier generation lifetime and the oxide capacitance in MOS structures. The method is demonstrated for an In0.53Ga0.47As system, but is generally applicable to any MOS structure exhibiting a minority carrier response in inversion.

Fabrication of sub-10 nm lamellar structures by solvent vapour annealing of block copolymers

Fabrication of nanoscale patterns through the bottom-up approach of self-assembly of phase-separated block copolymers (BCP) holds promise for nanoelectronics applications. For lithographic applications, it is useful to vary the morphology of BCPs by monitoring various parameters to make “from lab to fab” a reality. Here I report on the solvent annealing studies of lamellae forming polystyrene-blockpoly( 4-vinylpyridine) (PS-b-P4VP). The high Flory-Huggins parameter (χ = 0.34) of PS-b-P4VP makes it an ideal BCP system for self-assembly and template fabrication in comparison to other BCPs. Different molecular weights of symmetric PS-b-P4VP BCPs forming lamellae patterns were used to produce nanostructured thin films by spin-coating from mixture of toluene and tetrahydrofuran(THF). In particular, the morphology change from micellar structures to well-defined microphase separated arrangements is observed. Solvent annealing provides a better alternative to thermal treatment which often requires long annealing periods. The choice of solvent (single and dual solvent exposure) and the solvent annealing conditions have significant effects on the morphology of films and it was found that a block neutral solvent was required to realize vertically aligned PS and P4VP lamellae. Here, we have followed the formation of microdomain structures with time development at different temperatures by atomic force microscopy (AFM). The highly mobilized chains phase separate quickly due to high Flory-Huggins (χ) parameter. Ultra-small feature size (~10 nm pitch size) nanopatterns were fabricated by using low molecular weight PSb- P4VP (PS and P4VP blocks of 3.3 and 3.1 kg mol-1 respectively). However, due to the low etch contrast between the blocks, pattern transfer of the BCP mask is very challenging. To overcome the etch contrast problem, a novel and simple in-situ hard mask technology is used to fabricate the high aspect ratio silicon nanowires. The lamellar structures formed after self-assembly of phase separated PS-b-P4VP BCPs were used to fabricate iron oxide nanowires which acted as hard mask material to facilitate the pattern transfer into silicon and forming silicon nanostructures. The semiconductor and optical industries have shown significant interest in two dimensional (2D) molybdenum disulphide (MoS2) as a potential device material due to its low band gap and high mobility. However, current methods for its synthesis are not ‘fab’ friendly and require harsh environments and processes. Here, I also report a novel method to prepare MoS2 layered structures via self-assembly of a PS-b-P4VP block copolymer system. The formation of the layered MoS2 was confirmed by XPS, Raman spectroscopy and high resolution transmission electron microscopy.