Conceptual designs of multi-degree of freedom compliant parallel manipulators composed of wire-beam based compliant mechanisms

This paper proposes conceptual designs of multi-degree(s) of freedom (DOF) compliant parallel manipulators (CPMs) including 3-DOF translational CPMs and 6-DOF CPMs using a building block based pseudo-rigid-body-model (PRBM) approach. The proposed multi-DOF CPMs are composed of wire-beam based compliant mechanisms (WBBCMs) as distributed-compliance compliant building blocks (CBBs). Firstly, a comprehensive literature review for the design approaches of compliant mechanisms is conducted, and a building block based PRBM is then presented, which replaces the traditional kinematic sub-chain with an appropriate multi-DOF CBB. In order to obtain the decoupled 3-DOF translational CPMs (XYZ CPMs), two classes of kinematically decoupled 3-PPPR (P: prismatic joint, R: revolute joint) translational parallel mechanisms (TPMs) and 3-PPPRR TPMs are identified based on the type synthesis of rigid-body parallel mechanisms, and WBBCMs as the associated CBBs are further designed. Via replacing the traditional actuated P joint and the traditional passive PPR/PPRR sub-chain in each leg of the 3-DOF TPM with the counterpart CBBs (i.e. WBBCMs), a number of decoupled XYZ CPMs are obtained by appropriate arrangements. In order to obtain the decoupled 6-DOF CPMs, an orthogonally-arranged decoupled 6-PSS (S: spherical joint) parallel mechanism is first identified, and then two example 6-DOF CPMs are proposed by the building block based PRBM method. It is shown that, among these designs, two types of monolithic XYZ CPM designs with extended life have been presented.

The print block and the digital cylinder

Purpose – To consider the economic and physical impact of electronic journals on remotely stored print stock. Design/methodology/approach – A collection of print journals was used as an object for consideration. Physical and heritage aspects of the collection are examined and questions are posed regarding the wisdom of future retention in response to increased demand for electronic alternatives. Findings – Emerging trends predict a predominance of periodical literature in electronic form. The future of local remote storage for low demand printed journal collections needs to be evaluated in economic as well as cultural terms. Research limitations/implications – Based on a collection at the Boole Library, University College Cork, Ireland. Practical implications – Similar consideration should be given to collections in other regional libraries. Originality/value – Contributes to discussions on the long-term value of retaining print journal holdings.

Hardware design of cryptographic accelerators

With the rapid growth of the Internet and digital communications, the volume of sensitive electronic transactions being transferred and stored over and on insecure media has increased dramatically in recent years. The growing demand for cryptographic systems to secure this data, across a multitude of platforms, ranging from large servers to small mobile devices and smart cards, has necessitated research into low cost, flexible and secure solutions. As constraints on architectures such as area, speed and power become key factors in choosing a cryptosystem, methods for speeding up the development and evaluation process are necessary. This thesis investigates flexible hardware architectures for the main components of a cryptographic system. Dedicated hardware accelerators can provide significant performance improvements when compared to implementations on general purpose processors. Each of the designs proposed are analysed in terms of speed, area, power, energy and efficiency. Field Programmable Gate Arrays (FPGAs) are chosen as the development platform due to their fast development time and reconfigurable nature. Firstly, a reconfigurable architecture for performing elliptic curve point scalar multiplication on an FPGA is presented. Elliptic curve cryptography is one such method to secure data, offering similar security levels to traditional systems, such as RSA, but with smaller key sizes, translating into lower memory and bandwidth requirements. The architecture is implemented using different underlying algorithms and coordinates for dedicated Double-and-Add algorithms, twisted Edwards algorithms and SPA secure algorithms, and its power consumption and energy on an FPGA measured. Hardware implementation results for these new algorithms are compared against their software counterparts and the best choices for minimum area-time and area-energy circuits are then identified and examined for larger key and field sizes. Secondly, implementation methods for another component of a cryptographic system, namely hash functions, developed in the recently concluded SHA-3 hash competition are presented. Various designs from the three rounds of the NIST run competition are implemented on FPGA along with an interface to allow fair comparison of the different hash functions when operating in a standardised and constrained environment. Different methods of implementation for the designs and their subsequent performance is examined in terms of throughput, area and energy costs using various constraint metrics. Comparing many different implementation methods and algorithms is nontrivial. Another aim of this thesis is the development of generic interfaces used both to reduce implementation and test time and also to enable fair baseline comparisons of different algorithms when operating in a standardised and constrained environment. Finally, a hardware-software co-design cryptographic architecture is presented. This architecture is capable of supporting multiple types of cryptographic algorithms and is described through an application for performing public key cryptography, namely the Elliptic Curve Digital Signature Algorithm (ECDSA). This architecture makes use of the elliptic curve architecture and the hash functions described previously. These components, along with a random number generator, provide hardware acceleration for a Microblaze based cryptographic system. The trade-off in terms of performance for flexibility is discussed using dedicated software, and hardware-software co-design implementations of the elliptic curve point scalar multiplication block. Results are then presented in terms of the overall cryptographic system.

Block copolymer self-assembly based device structures

This thesis investigated the block copolymer (BCP) thin film characteristics and pattern formation using a set of predetermined molecular weights of PS-b-PMMA and PS-b-PDMS. Post BCP pattern fabrication on the required base substrate a dry plasma etch process was utilised for successful pattern transfer of the BCP resist onto underlying substrate. The resultant sub-10 nm device features were used in front end of line (FEoL) fabrication of active device components in integrated circuits (IC). The potential use of BCP templates were further extended to metal and metal-oxide nanowire fabrication. These nanowires were further investigated in real-time applications as novel sensors and supercapacitors.

Simplified decoding techniques for linear block codes

Error correcting codes are combinatorial objects, designed to enable reliable transmission of digital data over noisy channels. They are ubiquitously used in communication, data storage etc. Error correction allows reconstruction of the original data from received word. The classical decoding algorithms are constrained to output just one codeword. However, in the late 50’s researchers proposed a relaxed error correction model for potentially large error rates known as list decoding. The research presented in this thesis focuses on reducing the computational effort and enhancing the efficiency of decoding algorithms for several codes from algorithmic as well as architectural standpoint. The codes in consideration are linear block codes closely related to Reed Solomon (RS) codes. A high speed low complexity algorithm and architecture are presented for encoding and decoding RS codes based on evaluation. The implementation results show that the hardware resources and the total execution time are significantly reduced as compared to the classical decoder. The evaluation based encoding and decoding schemes are modified and extended for shortened RS codes and software implementation shows substantial reduction in memory footprint at the expense of latency. Hermitian codes can be seen as concatenated RS codes and are much longer than RS codes over the same aphabet. A fast, novel and efficient VLSI architecture for Hermitian codes is proposed based on interpolation decoding. The proposed architecture is proven to have better than Kötter’s decoder for high rate codes. The thesis work also explores a method of constructing optimal codes by computing the subfield subcodes of Generalized Toric (GT) codes that is a natural extension of RS codes over several dimensions. The polynomial generators or evaluation polynomials for subfield-subcodes of GT codes are identified based on which dimension and bound for the minimum distance are computed. The algebraic structure for the polynomials evaluating to subfield is used to simplify the list decoding algorithm for BCH codes. Finally, an efficient and novel approach is proposed for exploiting powerful codes having complex decoding but simple encoding scheme (comparable to RS codes) for multihop wireless sensor network (WSN) applications.

Application of semi-automated strain analysis techniques and anisotropy of magnetic susceptibility in fold and thrust belts

Quantitative analysis of penetrative deformation in sedimentary rocks of fold and thrust belts has largely been carried out using clast based strain analysis techniques. These methods analyse the geometric deviations from an original state that populations of clasts, or strain markers, have undergone. The characterisation of these geometric changes, or strain, in the early stages of rock deformation is not entirely straight forward. This is in part due to the paucity of information on the original state of the strain markers, but also the uncertainty of the relative rheological properties of the strain markers and their matrix during deformation, as well as the interaction of two competing fabrics, such as bedding and cleavage. Furthermore one of the single largest setbacks for accurate strain analysis has been associated with the methods themselves, they are traditionally time consuming, labour intensive and results can vary between users. A suite of semi-automated techniques have been tested and found to work very well, but in low strain environments the problems discussed above persist. Additionally these techniques have been compared to Anisotropy of Magnetic Susceptibility (AMS) analyses, which is a particularly sensitive tool for the characterisation of low strain in sedimentary lithologies.

Development of block copolymer lithography for device structure fabrication

This thesis investigated well-ordered block copolymer (BCP) thin film characteristics and their use for nanoscale pattern formation using a series of polystyrene-block-polymethylmethacrylate (PS-b-PMMA), polystyrene-blockpolydimethylsiloxane (PS-b-PDMS) and polystyrene-block-poly(ethylene oxide) (PS-b-PEO) systems of various molecular weights. BCP thin films, which act as an ‘on-chip’ etch mask and material templates, are highly promising self-assembling process for future scalable nanolithography. Unlike conventional BCP processing methods, the work in this thesis demonstrates that well-ordered patterns can be achieved in a few seconds compared to several hours by use of a non-conventional microwave assisted technique. As a result, well-ordered BCP nanoscale structures can be developed in industry appropriate periods facilitating their incorporation into current technologies. An optimised and controlled plasma dry etch process was used for successful pattern transfer to the underlying silicon substrate. Long range ordered BCP templates were further modified by selective metal inclusion technique to form a hard mask template towards fabrication of high aspect ratio nanopillars and nanowires. The work described here is centred on how these templates might be used to generate function at substrate surfaces. Herein we describe a number of innovations which might allow their successful uptake in a number of applications.

Insertion of metal oxides into block copolymer nanopatterns as robust etch masks for nanolithography

Directed self-assembly (DSA) of block copolymers (BCPs) is a prime candidate to further extend dimensional scaling of silicon integrated circuit features for the nanoelectronic industry. Top-down optical techniques employed for photoresist patterning are predicted to reach an endpoint due to diffraction limits. Additionally, the prohibitive costs for “fabs” and high volume manufacturing tools are issues that have led the search for alternative complementary patterning processes. This thesis reports the fabrication of semiconductor features from nanoscale on-chip etch masks using “high χ” BCP materials. Fabrication of silicon and germanium nanofins via metal-oxide enhanced BCP on-chip etch masks that might be of importance for future Fin-field effect transistor (FinFETs) application are detailed.