Creation of a complex butterfly attractor using a novel Lorenz-type system

A novel Lorenz-type system of nonlinear differential equations is proposed. Unlike the original Lorenz system, where the chaotic dynamics remain confined to the positive half-space with respect to the Z state variable due to a limiting threshold effect, the proposed system enables bipolar swing of this state variable. In addition, the classical set of parameters (a, b, c) controlling the behavior of the Lorenz system are reduced to a single parameter, namely a. Two possible modes of operation are admitted by the system; switching between these two modes results in the creation of a complex butterfly chaotic attractor. Numerical simulations and results from an experimental setup are presented

Carbon nanotubes as materials in nanotechnology

Carbon nanotubes (CNTs) are hollow tubes of sp2-hybridised carbon with diameters of the order of nanometres. Due to their unique physical properties, which include ballistic transport and high mechanical strength, they are of significant interest for technological applications. The electronic properties of CNTs are of particular interest for use as gas sensors, interconnect materials in the semi-conductor industry and as the channel material in CNT based field effect transistors. The primary difficulty associated with the use of CNTs in electronic applications is the inability to control electronic properties at the growth stage; as grown CNTs consist of a mixture of metallic and semi-conducting CNTs. Doping has the potential to solve this problem and is a focus of this thesis. Nitrogen-doped CNTs typically have defective structures; the usual hollow CNT structure is replaced by a series of compartments. Through density functional theory (DFT) calculations and experimental results, we propose an explanation for the defective structures obtained, based on the stronger binding of N to the growth catalyst in comparison to C. In real electronic devices, CNTs need to be contacted to metal, we generate the current-voltage (IV) characteristics of metal-contacted CNTs considering both the effect of dopants and the structure of the interface region on electronic properties. We find that substitutionally doped CNTs produce Ohmic contacts and that scattering at the interface is strongly influenced by structure. In addition, we consider the effect of the common vacancy defects on the electronic properties of large diameter CNTs. Defects increase scattering in the CNT, with the greatest scattering occurring for the largest defect (555777). We validate the independent scattering approximation for small diameter CNTs, which enables mean free paths in large diameter CNTs to be calculated, with a smaller mean free paths found for larger defects.

Development of inversion-mode and junctionless Indium-Gallium-Arsenide MOSFETs

This PhD covers the development of planar inversion-mode and junctionless Al2O3/In0.53Ga0.47As metal-oxidesemiconductor field-effect transistors (MOSFETs). An implant activation anneal was developed for the formation of the source and drain (S/D) of the inversionmode MOSFET. Fabricated inversion-mode devices were used as test vehicles to investigate the impact of forming gas annealing (FGA) on device performance. Following FGA, the devices exhibited a subthreshold swing (SS) of 150mV/dec., an ION/IOFF of 104 and the transconductance, drive current and peak effective mobility increased by 29%, 25% and 15%, respectively. An alternative technique, based on the fitting of the measured full-gate capacitance vs gate voltage using a selfconsistent Poisson-Schrödinger solver, was developed to extract the trap energy profile across the full In0.53Ga0.47As bandgap and beyond. A multi-frequency inversion-charge pumping approach was proposed to (1) study the traps located at energy levels aligned with the In0.53Ga0.47As conduction band and (2) separate the trapped charge and mobile charge contributions. The analysis revealed an effective mobility (μeff) peaking at ~2850cm2/V.s for an inversion-charge density (Ninv) = 7*1011cm2 and rapidly decreasing to ~600cm2/V.s for Ninv = 1*1013 cm2, consistent with a μeff limited by surface roughness scattering. Atomic force microscopy measurements confirmed a large surface roughness of 1.95±0.28nm on the In0.53Ga0.47As channel caused by the S/D activation anneal. In order to circumvent the issue relative to S/D formation, a junctionless In0.53Ga0.47As device was developed. A digital etch was used to thin the In0.53Ga0.47As channel and investigate the impact of channel thickness (tInGaAs) on device performance. Scaling of the SS with tInGaAs was observed for tInGaAs going from 24 to 16nm, yielding a SS of 115mV/dec. for tInGaAs = 16nm. Flat-band μeff values of 2130 and 1975cm2/V.s were extracted on devices with tInGaAs of 24 and 20nm, respectively

Effects of alternating current voltage amplitude and oxide capacitance on mid-gap interface state defect density extractions in In0.53Ga 0.47As capacitors

This work looks at the effect on mid-gap interface state defect density estimates for In0.53Ga0.47As semiconductor capacitors when different AC voltage amplitudes are selected for a fixed voltage bias step size (100 mV) during room temperature only electrical characterization. Results are presented for Au/Ni/Al2O3/In0.53Ga0.47As/InP metal–oxide–semiconductor capacitors with (1) n-type and p-type semiconductors, (2) different Al2O3 thicknesses, (3) different In0.53Ga0.47As surface passivation concentrations of ammonium sulphide, and (4) different transfer times to the atomic layer deposition chamber after passivation treatment on the semiconductor surface—thereby demonstrating a cross-section of device characteristics. The authors set out to determine the importance of the AC voltage amplitude selection on the interface state defect density extractions and whether this selection has a combined effect with the oxide capacitance. These capacitors are prototypical of the type of gate oxide material stacks that could form equivalent metal–oxide–semiconductor field-effect transistors beyond the 32 nm technology node. The authors do not attempt to achieve the best scaled equivalent oxide thickness in this work, as our focus is on accurately extracting device properties that will allow the investigation and reduction of interface state defect densities at the high-k/III–V semiconductor interface. The operating voltage for future devices will be reduced, potentially leading to an associated reduction in the AC voltage amplitude, which will force a decrease in the signal-to-noise ratio of electrical responses and could therefore result in less accurate impedance measurements. A concern thus arises regarding the accuracy of the electrical property extractions using such impedance measurements for future devices, particularly in relation to the mid-gap interface state defect density estimated from the conductance method and from the combined high–low frequency capacitance–voltage method. The authors apply a fixed voltage step of 100 mV for all voltage sweep measurements at each AC frequency. Each of these measurements is repeated 15 times for the equidistant AC voltage amplitudes between 10 mV and 150 mV. This provides the desired AC voltage amplitude to step size ratios from 1:10 to 3:2. Our results indicate that, although the selection of the oxide capacitance is important both to the success and accuracy of the extraction method, the mid-gap interface state defect density extractions are not overly sensitive to the AC voltage amplitude employed regardless of what oxide capacitance is used in the extractions, particularly in the range from 50% below the voltage sweep step size to 50% above it. Therefore, the use of larger AC voltage amplitudes in this range to achieve a better signal-to-noise ratio during impedance measurements for future low operating voltage devices will not distort the extracted interface state defect density.

Organic functionalisation, doping and characterisation of semiconductor surfaces for future CMOS device applications

Organic Functionalisation, Doping and Characterisation of Semiconductor Surfaces for Future CMOS Device Applications Semiconductor materials have long been the driving force for the advancement of technology since their inception in the mid-20th century. Traditionally, micro-electronic devices based upon these materials have scaled down in size and doubled in transistor density in accordance with the well-known Moore’s law, enabling consumer products with outstanding computational power at lower costs and with smaller footprints. According to the International Technology Roadmap for Semiconductors (ITRS), the scaling of metal-oxide-semiconductor field-effect transistors (MOSFETs) is proceeding at a rapid pace and will reach sub-10 nm dimensions in the coming years. This scaling presents many challenges, not only in terms of metrology but also in terms of the material preparation especially with respect to doping, leading to the moniker “More-than-Moore”. Current transistor technologies are based on the use of semiconductor junctions formed by the introduction of dopant atoms into the material using various methodologies and at device sizes below 10 nm, high concentration gradients become a necessity. Doping, the controlled and purposeful addition of impurities to a semiconductor, is one of the most important steps in the material preparation with uniform and confined doping to form ultra-shallow junctions at source and drain extension regions being one of the key enablers for the continued scaling of devices. Monolayer doping has shown promise to satisfy the need to conformally dope at such small feature sizes. Monolayer doping (MLD) has been shown to satisfy the requirements for extended defect-free, conformal and controllable doping on many materials ranging from the traditional silicon and germanium devices to emerging replacement materials such as III-V compounds This thesis aims to investigate the potential of monolayer doping to complement or replace conventional doping technologies currently in use in CMOS fabrication facilities across the world.