The impact of maternal inflammation and maternal stress in the regulation of neurodevelopment and physiological function

The mechanisms governing fetal development follow a tightly regulated pattern of progression such that interference at any one particular stage is likely to have consequences for all other stages of development in the physiological system that has been affected thereafter. These disturbances can take the form of many different events but two of the most common and widely implicated in causing detrimental effects to the developing fetus are maternal immune activation (MIA) and maternal stress. MIA has been shown to cause an increase in circulating proinflammatory cytokines in both the maternal and fetal circulation. This increase in proinflammatory mediators in the fetus is thought to occur by fetal production rather than through exchange between the maternal-fetal interface. In the case of maternal stress it is increased levels of stress related hormones such as cortisol/corticosterone which is thought to elicit the detrimental effects on fetal development. In the case of both maternal infection and stress the timing and nature of the insult generally dictates the severity and type of effects seen in affected offspring. We investigated the effect of a proinflammatory environment on neural precursor cells of which exposure resulted in a significant decrease in the normal rate of proliferation of NPCs in culture but did not have any effect on cell survival. These effects were seen to be age dependent. Using a restraint stress model we investigated the effects of prenatal stress on the development of a number of different physiological systems in the same cohort of animals. PNS animals exhibited a number of aberrant changes in cardiovascular function with altered responses to stress and hypertension, modifications in respiratory responses to hypercapnic and hypoxic challenges and discrepancies in gastrointestinal innervation. Taken together these findings suggest that both maternal infection and maternal stress are detrimental to the normal development of the fetus.

County Cork: the experience of members of the establishment whose houses were burned in the IRA arson campaign, 1920-23

Between May 1920 and March 1923, there were seventy-three houses belonging to the County Cork establishment burnt down by IRA and anti-treaty forces. More houses were destroyed by this method in Cork than in any other Irish county in the same timeframe. The establishment were targeted by the IRA for their political, military and social persuasions that were essentially in opposition to the nationalist movement. The motivations behind these burnings is examined, the main reasons being reprisals for actions taken by Crown forces, military reasons, loyalty of house owners to the British government and agrarianism. The geographical distribution of these burnings is also provided to reveal how active individual IRA brigades were that operated within the county. Though there were few areas of the county left unaffected by the occurrence of arson attacks, there were higher concentrations of burnings in some areas. The house burnings in County Cork did not conform to the national pattern of house burnings and the reasons for this are explored. This study argues that the presence of Crown forces in Cork and their implementation of an official reprisal policy in January 1921 escalated military conflict, and arson attacks became a key tactic utilised by IRA forces in response to this policy. The aftermath of house burnings for members of the establishment is revealed through the various compensation committees that were formed after both the War of Independence and Civil War. Key sources for this study included personal papers of both the establishment and military figures, IRA witness statements, local and national newspapers, the 1901 and 1911 Irish Censuses, Colonial Office Papers, compensation claims filed with the British government and Irish Free State, and others from archives throughout Ireland and the United Kingdom.

Average-case analysis of power consumption in embedded systems

Power efficiency is one of the most important constraints in the design of embedded systems since such systems are generally driven by batteries with limited energy budget or restricted power supply. In every embedded system, there are one or more processor cores to run the software and interact with the other hardware components of the system. The power consumption of the processor core(s) has an important impact on the total power dissipated in the system. Hence, the processor power optimization is crucial in satisfying the power consumption constraints, and developing low-power embedded systems. A key aspect of research in processor power optimization and management is “power estimation”. Having a fast and accurate method for processor power estimation at design time helps the designer to explore a large space of design possibilities, to make the optimal choices for developing a power efficient processor. Likewise, understanding the processor power dissipation behaviour of a specific software/application is the key for choosing appropriate algorithms in order to write power efficient software. Simulation-based methods for measuring the processor power achieve very high accuracy, but are available only late in the design process, and are often quite slow. Therefore, the need has arisen for faster, higher-level power prediction methods that allow the system designer to explore many alternatives for developing powerefficient hardware and software. The aim of this thesis is to present fast and high-level power models for the prediction of processor power consumption. Power predictability in this work is achieved in two ways: first, using a design method to develop power predictable circuits; second, analysing the power of the functions in the code which repeat during execution, then building the power model based on average number of repetitions. In the first case, a design method called Asynchronous Charge Sharing Logic (ACSL) is used to implement the Arithmetic Logic Unit (ALU) for the 8051 microcontroller. The ACSL circuits are power predictable due to the independency of their power consumption to the input data. Based on this property, a fast prediction method is presented to estimate the power of ALU by analysing the software program, and extracting the number of ALU-related instructions. This method achieves less than 1% error in power estimation and more than 100 times speedup in comparison to conventional simulation-based methods. In the second case, an average-case processor energy model is developed for the Insertion sort algorithm based on the number of comparisons that take place in the execution of the algorithm. The average number of comparisons is calculated using a high level methodology called MOdular Quantitative Analysis (MOQA). The parameters of the energy model are measured for the LEON3 processor core, but the model is general and can be used for any processor. The model has been validated through the power measurement experiments, and offers high accuracy and orders of magnitude speedup over the simulation-based method.