Systematic delay-driven power optimisation and power-driven delay optimisation of combinational circuits

With the proliferation of mobile wireless communication and embedded systems, the energy efficiency becomes a major design constraint. The dissipated energy is often referred as the product of power dissipation and the input-output delay. Most of electronic design automation techniques focus on optimising only one of these parameters either power or delay. Industry standard design flows integrate systematic methods of optimising either area or timing while for power consumption optimisation one often employs heuristics which are characteristic to a specific design. In this work we answer three questions in our quest to provide a systematic approach to joint power and delay Optimisation. The first question of our research is: How to build a design flow which incorporates academic and industry standard design flows for power optimisation? To address this question, we use a reference design flow provided by Synopsys and integrate in this flow academic tools and methodologies. The proposed design flow is used as a platform for analysing some novel algorithms and methodologies for optimisation in the context of digital circuits. The second question we answer is: Is possible to apply a systematic approach for power optimisation in the context of combinational digital circuits? The starting point is a selection of a suitable data structure which can easily incorporate information about delay, power, area and which then allows optimisation algorithms to be applied. In particular we address the implications of a systematic power optimisation methodologies and the potential degradation of other (often conflicting) parameters such as area or the delay of implementation. Finally, the third question which this thesis attempts to answer is: Is there a systematic approach for multi-objective optimisation of delay and power? A delay-driven power and power-driven delay optimisation is proposed in order to have balanced delay and power values. This implies that each power optimisation step is not only constrained by the decrease in power but also the increase in delay. Similarly, each delay optimisation step is not only governed with the decrease in delay but also the increase in power. The goal is to obtain multi-objective optimisation of digital circuits where the two conflicting objectives are power and delay. The logic synthesis and optimisation methodology is based on AND-Inverter Graphs (AIGs) which represent the functionality of the circuit. The switching activities and arrival times of circuit nodes are annotated onto an AND-Inverter Graph under the zero and a non-zero-delay model. We introduce then several reordering rules which are applied on the AIG nodes to minimise switching power or longest path delay of the circuit at the pre-technology mapping level. The academic Electronic Design Automation (EDA) tool ABC is used for the manipulation of AND-Inverter Graphs. We have implemented various combinatorial optimisation algorithms often used in Electronic Design Automation such as Simulated Annealing and Uniform Cost Search Algorithm. Simulated Annealing (SMA) is a probabilistic meta heuristic for the global optimization problem of locating a good approximation to the global optimum of a given function in a large search space. We used SMA to probabilistically decide between moving from one optimised solution to another such that the dynamic power is optimised under given delay constraints and the delay is optimised under given power constraints. A good approximation to the global optimum solution of energy constraint is obtained. Uniform Cost Search (UCS) is a tree search algorithm used for traversing or searching a weighted tree, tree structure, or graph. We have used Uniform Cost Search Algorithm to search within the AIG network, a specific AIG node order for the reordering rules application. After the reordering rules application, the AIG network is mapped to an AIG netlist using specific library cells. Our approach combines network re-structuring, AIG nodes reordering, dynamic power and longest path delay estimation and optimisation and finally technology mapping to an AIG netlist. A set of MCNC Benchmark circuits and large combinational circuits up to 100,000 gates have been used to validate our methodology. Comparisons for power and delay optimisation are made with the best synthesis scripts used in ABC. Reduction of 23% in power and 15% in delay with minimal overhead is achieved, compared to the best known ABC results. Also, our approach is also implemented on a number of processors with combinational and sequential components and significant savings are achieved.

Caesarean section and subsequent pregnancy outcome: a Danish register-based cohort study

Background and Aims: Caesarean section rates have increased in recent decades and the effects on subsequent pregnancy outcome are largely unknown. Prior research has hypothesised that Caesarean section delivery may lead to an increased risk of subsequent stillbirth, miscarriage, ectopic pregnancy and sub-fertility. Structure and Methods: Papers 1-3 are systematic reviews with meta-analyses. Papers 4-6 are findings from this thesis on the rate of subsequent stillbirth, miscarriage, ectopic pregnancy and live birth by mode of delivery. Results Systematic reviews and meta-analyses: A 23% increased odds of subsequent stillbirth; no increase in odds of subsequent ectopic pregnancy and a 10% reduction in the odds of subsequent live birth among women with a previous Caesarean section were found in the various meta-analyses. Danish cohorts: Results from the Danish Civil Registration System (CRS) cohort revealed a small increased rate of subsequent stillbirth and ectopic pregnancy among women with a primary Caesarean section, which remained in the analyses by type of Caesarean. No increased rate of miscarriage was found among women with a primary Caesarean section. In the CRS data, women with a primary Caesarean section had a significantly reduced rate of subsequent live birth particularly among women with primary elective and maternal-requested Caesarean sections. In the Aarhus Birth Cohort, overall the effect of mode of delivery on the rate and time to next live birth was minimal. Conclusions: Primary Caesarean section was associated with a small increased rate of stillbirth and ectopic pregnancy, which may be in part due to underlying medical conditions. No increased rate of miscarriage was found. A reduced rate of subsequent live birth was found among Caesarean section in the CRS data. In the smaller ABC cohort, a small reduction in rate of subsequent live birth was found among women with a primary Caesarean section and is most likely due to maternal choice rather than any ill effects of the Caesarean. The findings of this study, the largest and most comprehensive to date will be of significant interest to health care providers and women globally.

Thuricin CD: a potential therapeutic targeted against Clostridium difficile-associated diarrhea (CDAD)

Clostridium difficile is mainly a nosocomial pathogen and is a significant cause of antibioticassociated diarrhea. It is also implicated in the majority of cases of pseudomembranous colitis. The main etiological agent of C. difficile-associated diarrhea (CDAD) is perturbations to the gut microbiota by broad-spectrum antibiotics. Recently, thuricin CD, a two-peptide narrow spectrum sactibiotic bacteriocin with potent activity against C. difficile has been discovered. It is produced by Bacillus thuringiensis DPC6431. The efficacy of thuricin CD against a range of C. difficile clinical isolates has been determined in the form of minimum inhibitory concentration (MIC) values and compared to metronidazole, vancomycin, ramoplanin and actagardine in this thesis. Furthermore, by assessing paired combinations of the above-mentioned antimicrobials, it was determined that ramoplanin and actagardine function in a synergistic manner against the majority of C. difficile isolates. The functions of the genes in the thuricin CD gene cluster have also been elucidated by cloning the cluster and expressing thuricin CD in a heterologous Bacillus subtilis host and are described herein. In addition, the immunity mechanisms employed by the B. thuringiensis DPC6431 producer to protect itself from the antimicrobial actions of thuricin CD have also been elucidated. It has been shown that a small immunity peptide, TrnI, is involved in thuricin CD immunity, most likely by intercepting the thuricin CD peptides and/or blocking their access to the thuricin CD receptor. This immunity peptide and also the ABC-transporter system TrnFG serve to protect the B. thuringiensis host against thuricin CD.