Effects of alternating current voltage amplitude and oxide capacitance on mid-gap interface state defect density extractions in In0.53Ga 0.47As capacitors

This work looks at the effect on mid-gap interface state defect density estimates for In0.53Ga0.47As semiconductor capacitors when different AC voltage amplitudes are selected for a fixed voltage bias step size (100 mV) during room temperature only electrical characterization. Results are presented for Au/Ni/Al2O3/In0.53Ga0.47As/InP metal–oxide–semiconductor capacitors with (1) n-type and p-type semiconductors, (2) different Al2O3 thicknesses, (3) different In0.53Ga0.47As surface passivation concentrations of ammonium sulphide, and (4) different transfer times to the atomic layer deposition chamber after passivation treatment on the semiconductor surface—thereby demonstrating a cross-section of device characteristics. The authors set out to determine the importance of the AC voltage amplitude selection on the interface state defect density extractions and whether this selection has a combined effect with the oxide capacitance. These capacitors are prototypical of the type of gate oxide material stacks that could form equivalent metal–oxide–semiconductor field-effect transistors beyond the 32 nm technology node. The authors do not attempt to achieve the best scaled equivalent oxide thickness in this work, as our focus is on accurately extracting device properties that will allow the investigation and reduction of interface state defect densities at the high-k/III–V semiconductor interface. The operating voltage for future devices will be reduced, potentially leading to an associated reduction in the AC voltage amplitude, which will force a decrease in the signal-to-noise ratio of electrical responses and could therefore result in less accurate impedance measurements. A concern thus arises regarding the accuracy of the electrical property extractions using such impedance measurements for future devices, particularly in relation to the mid-gap interface state defect density estimated from the conductance method and from the combined high–low frequency capacitance–voltage method. The authors apply a fixed voltage step of 100 mV for all voltage sweep measurements at each AC frequency. Each of these measurements is repeated 15 times for the equidistant AC voltage amplitudes between 10 mV and 150 mV. This provides the desired AC voltage amplitude to step size ratios from 1:10 to 3:2. Our results indicate that, although the selection of the oxide capacitance is important both to the success and accuracy of the extraction method, the mid-gap interface state defect density extractions are not overly sensitive to the AC voltage amplitude employed regardless of what oxide capacitance is used in the extractions, particularly in the range from 50% below the voltage sweep step size to 50% above it. Therefore, the use of larger AC voltage amplitudes in this range to achieve a better signal-to-noise ratio during impedance measurements for future low operating voltage devices will not distort the extracted interface state defect density.

Organic functionalisation, doping and characterisation of semiconductor surfaces for future CMOS device applications

Organic Functionalisation, Doping and Characterisation of Semiconductor Surfaces for Future CMOS Device Applications Semiconductor materials have long been the driving force for the advancement of technology since their inception in the mid-20th century. Traditionally, micro-electronic devices based upon these materials have scaled down in size and doubled in transistor density in accordance with the well-known Moore’s law, enabling consumer products with outstanding computational power at lower costs and with smaller footprints. According to the International Technology Roadmap for Semiconductors (ITRS), the scaling of metal-oxide-semiconductor field-effect transistors (MOSFETs) is proceeding at a rapid pace and will reach sub-10 nm dimensions in the coming years. This scaling presents many challenges, not only in terms of metrology but also in terms of the material preparation especially with respect to doping, leading to the moniker “More-than-Moore”. Current transistor technologies are based on the use of semiconductor junctions formed by the introduction of dopant atoms into the material using various methodologies and at device sizes below 10 nm, high concentration gradients become a necessity. Doping, the controlled and purposeful addition of impurities to a semiconductor, is one of the most important steps in the material preparation with uniform and confined doping to form ultra-shallow junctions at source and drain extension regions being one of the key enablers for the continued scaling of devices. Monolayer doping has shown promise to satisfy the need to conformally dope at such small feature sizes. Monolayer doping (MLD) has been shown to satisfy the requirements for extended defect-free, conformal and controllable doping on many materials ranging from the traditional silicon and germanium devices to emerging replacement materials such as III-V compounds This thesis aims to investigate the potential of monolayer doping to complement or replace conventional doping technologies currently in use in CMOS fabrication facilities across the world.

Giant enhancement of n-type carrier mobility in highly strained germanium nanostructures

First-principles electronic structure methods are used to predict the rate of n-type carrier scattering due to phonons in highly-strained Ge. We show that strains achievable in nanoscale structures, where Ge becomes a direct bandgap semiconductor, cause the phonon-limited mobility to be enhanced by hundreds of times that of unstrained Ge, and over a thousand times that of Si. This makes highly tensile strained Ge a most promising material for the construction of channels in CMOS devices, as well as for Si-based photonic applications. Biaxial (001) strain achieves mobility enhancements of 100 to 1000 with strains over 2%. Low temperature mobility can be increased by even larger factors. Second order terms in the deformation potential of the Gamma valley are found to be important in this mobility enhancement. Although they are modified by shifts in the conduction band valleys, which are caused by carrier quantum confinement, these mobility enhancements persist in strained nanostructures down to sizes of 20 nm.

Large magnetoelectric coupling in nanoscale BiFeO3 from direct electrical measurements

We report the results of direct measurement of remanent hysteresis loops on nanochains of BiFeO3 at room temperature under zero and ∼20 kOe magnetic field. We noticed a suppression of remanent polarization by nearly ∼40% under the magnetic field. The powder neutron diffraction data reveal significant ion displacements under a magnetic field which seems to be the origin of the suppression of polarization. The isolated nanoparticles, comprising the chains, exhibit evolution of ferroelectric domains under dc electric field and complete 180 switching in switching-spectroscopy piezoresponse force microscopy. They also exhibit stronger ferromagnetism with nearly an order of magnitude higher saturation magnetization than that of the bulk sample. These results show that the nanoscale BiFeO3 exhibits coexistence of ferroelectric and ferromagnetic order and a strong magnetoelectric multiferroic coupling at room temperature comparable to what some of the type-II multiferroics show at a very low temperature.