Development of CMOS-compatible electrostatic supercapacitors

This work focuses on development of electrostatic supercapacitors (ESCs) using process routes compatible with complementary metal–oxide–semiconductor (CMOS) fabrication. Wafer-scale anodised aluminium oxide (AAO) processing techniques have been developed to produce high-surface area templates. Statistically optimised atomic layer deposition (ALD) processes have been developed to conformally coat the templates and generate metalinsulator-metal capacitor structures. Detailed electrical characterisation and analysis for a range of devices, revealed ESC’s with high capacitance densities of ~12 μF cm-2 and equivalent energy densities of 0.28 Wh/kg . Finally the suitability of ESC’s toward next generation energy storage applications is discussed.

Atomic layer deposition of copper for CMOS interconnects

This work concerns the atomic layer deposition (ALD) of copper. ALD is a technique that allows conformal coating of difficult topographies such as narrow trenches and holes or even shadowed regions. However, the deposition of pure metals has so far been less successful than the deposition of oxides except for a few exceptions. Challenges include difficulties associated with the reduction of the metal centre of the precursor at reasonable temperatures and the tendency of metals to agglomerate during the growth process. Cu is a metal of special technical interest as it is widely used for interconnects on CMOS devices. These interconnects are usually fabricated by electroplating, which requires the deposition of thin Cu seed layers onto the trenches and vias. Here, ALD is regarded as potential candidate for replacing the current PVD technique, which is expected to reach its limitations as the critical dimensions continue to shrink. This work is separated into two parts. In the first part, a laboratory-scale ALD reactor was constructed and used for the thermal ALD of Cu. In the second part, the potentials of the application of Cu ALD on industry scale fabrication were examined in a joint project with Applied Materials and Intel. Within this project precursors developed by industrial partners were evaluated on a 300 mm Applied Materials metal-ALD chamber modified with a direct RF-plasma source. A feature that makes ALD a popular technique among researchers is the possibility to produce high- level thin film coatings for micro-electronics and nano-technology with relatively simple laboratory- scale reactors. The advanced materials and surfaces group (AMSG) at Tyndall National Institute operates a range of home-built ALD reactors. In order to carry out Cu ALD experiments, modifications to the normal reactor design had to be made. For example a carrier gas mechanism was necessary to facilitate the transport of the low-volatile Cu precursors. Precursors evaluated included the readily available Cu(II)-diketonates Cu-bis(acetylacetonate), Cu-bis(2,2,6,6-tetramethyl-hepta-3,5-dionate) and Cu-bis(1,1,1,5,5,5-hexafluoacetylacetonate) as well as the Cu-ketoiminate Cu-bis(4N-ethylamino- pent-3-en-2-onate), which is also known under the trade name AbaCus (Air Liquide), and the Cu(I)- silylamide 1,3-diisopropyl-imidazolin-2-ylidene Cu(I) hexamethyldisilazide ([NHC]Cu(hmds)), which was developed at Carleton University Ottawa. Forming gas (10 % H2 in Ar) was used as reducing agent except in early experiments where formalin was used. With all precursors an extreme surface selectivity of the deposition process was observed and significant growth was only achieved on platinum-group metals. Improvements in the Cu deposition process were obtained with [NHC]Cu(hmds) compared with the Cu(II) complexes. A possible reason is the reduced oxidation state of the metal centre. Continuous Cu films were obtained on Pd and indications for saturated growth with a rate of about 0.4 Å/cycle were found for deposition at 220 °C. Deposits obtained on Ru consisted of separated islands. Although no continuous films could be obtained in this work the relatively high density of Cu islands obtained was a clear improvement as compared to the deposits grown with Cu(II) complexes. When ultra-thin Pd films were used as substrates, island growth was also observed. A likely reason for this extreme difference to the Cu films obtained on thicker Pd films is the lack of stress compensation within the thin films. The most likely source of stress compensation in the thicker Pd films is the formation of a graded interlayer between Pd and Cu by inter-diffusion. To obtain continuous Cu films on more materials, reduction of the growth temperature was required. This was achieved in the plasma assisted ALD experiments discussed in the second part of this work. The precursors evaluated included the AbaCus compound and CTA-1, an aliphatic Cu-bis(aminoalkoxide), which was supplied by Adeka Corp.. Depositions could be carried out at very low temperatures (60 °C Abacus, 30 °C CTA-1). Metallic Cu could be obtained on all substrate materials investigated, but the shape of the deposits varied significantly between the substrate materials. On most materials (Si, TaN, Al2O3, CDO) Cu grew in isolated nearly spherical islands even at temperatures as low as 30 °C. It was observed that the reason for the island formation is the coalescence of the initial islands to larger, spherical islands instead of forming a continuous film. On the other hand, the formation of nearly two-dimensional islands was observed on Ru. These islands grew together forming a conductive film after a reasonably small number of cycles. The resulting Cu films were of excellent crystal quality and had good electrical properties; e.g. a resistivity of 2.39 µΩ cm was measured for a 47 nm thick film. Moreover, conformal coating of narrow trenches (1 µm deep 100/1 aspect ratio) was demonstrated showing the feasibility of the ALD process.

Effects of alternating current voltage amplitude and oxide capacitance on mid-gap interface state defect density extractions in In0.53Ga 0.47As capacitors

This work looks at the effect on mid-gap interface state defect density estimates for In0.53Ga0.47As semiconductor capacitors when different AC voltage amplitudes are selected for a fixed voltage bias step size (100 mV) during room temperature only electrical characterization. Results are presented for Au/Ni/Al2O3/In0.53Ga0.47As/InP metal–oxide–semiconductor capacitors with (1) n-type and p-type semiconductors, (2) different Al2O3 thicknesses, (3) different In0.53Ga0.47As surface passivation concentrations of ammonium sulphide, and (4) different transfer times to the atomic layer deposition chamber after passivation treatment on the semiconductor surface—thereby demonstrating a cross-section of device characteristics. The authors set out to determine the importance of the AC voltage amplitude selection on the interface state defect density extractions and whether this selection has a combined effect with the oxide capacitance. These capacitors are prototypical of the type of gate oxide material stacks that could form equivalent metal–oxide–semiconductor field-effect transistors beyond the 32 nm technology node. The authors do not attempt to achieve the best scaled equivalent oxide thickness in this work, as our focus is on accurately extracting device properties that will allow the investigation and reduction of interface state defect densities at the high-k/III–V semiconductor interface. The operating voltage for future devices will be reduced, potentially leading to an associated reduction in the AC voltage amplitude, which will force a decrease in the signal-to-noise ratio of electrical responses and could therefore result in less accurate impedance measurements. A concern thus arises regarding the accuracy of the electrical property extractions using such impedance measurements for future devices, particularly in relation to the mid-gap interface state defect density estimated from the conductance method and from the combined high–low frequency capacitance–voltage method. The authors apply a fixed voltage step of 100 mV for all voltage sweep measurements at each AC frequency. Each of these measurements is repeated 15 times for the equidistant AC voltage amplitudes between 10 mV and 150 mV. This provides the desired AC voltage amplitude to step size ratios from 1:10 to 3:2. Our results indicate that, although the selection of the oxide capacitance is important both to the success and accuracy of the extraction method, the mid-gap interface state defect density extractions are not overly sensitive to the AC voltage amplitude employed regardless of what oxide capacitance is used in the extractions, particularly in the range from 50% below the voltage sweep step size to 50% above it. Therefore, the use of larger AC voltage amplitudes in this range to achieve a better signal-to-noise ratio during impedance measurements for future low operating voltage devices will not distort the extracted interface state defect density.

Organic functionalisation, doping and characterisation of semiconductor surfaces for future CMOS device applications

Organic Functionalisation, Doping and Characterisation of Semiconductor Surfaces for Future CMOS Device Applications Semiconductor materials have long been the driving force for the advancement of technology since their inception in the mid-20th century. Traditionally, micro-electronic devices based upon these materials have scaled down in size and doubled in transistor density in accordance with the well-known Moore’s law, enabling consumer products with outstanding computational power at lower costs and with smaller footprints. According to the International Technology Roadmap for Semiconductors (ITRS), the scaling of metal-oxide-semiconductor field-effect transistors (MOSFETs) is proceeding at a rapid pace and will reach sub-10 nm dimensions in the coming years. This scaling presents many challenges, not only in terms of metrology but also in terms of the material preparation especially with respect to doping, leading to the moniker “More-than-Moore”. Current transistor technologies are based on the use of semiconductor junctions formed by the introduction of dopant atoms into the material using various methodologies and at device sizes below 10 nm, high concentration gradients become a necessity. Doping, the controlled and purposeful addition of impurities to a semiconductor, is one of the most important steps in the material preparation with uniform and confined doping to form ultra-shallow junctions at source and drain extension regions being one of the key enablers for the continued scaling of devices. Monolayer doping has shown promise to satisfy the need to conformally dope at such small feature sizes. Monolayer doping (MLD) has been shown to satisfy the requirements for extended defect-free, conformal and controllable doping on many materials ranging from the traditional silicon and germanium devices to emerging replacement materials such as III-V compounds This thesis aims to investigate the potential of monolayer doping to complement or replace conventional doping technologies currently in use in CMOS fabrication facilities across the world.

VAMP - a vision based sensor network for health care hygiene

Adequate hand-washing has been shown to be a critical activity in preventing the transmission of infections such as MRSA in health-care environments. Hand-washing guidelines published by various health-care related institutions recommend a technique incorporating six hand-washing poses that ensure all areas of the hands are thoroughly cleaned. In this paper, an embedded wireless vision system (VAMP) capable of accurately monitoring hand-washing quality is presented. The VAMP system hardware consists of a low resolution CMOS image sensor and FPGA processor which are integrated with a microcontroller and ZigBee standard wireless transceiver to create a wireless sensor network (WSN) based vision system that can be retargeted at a variety of health care applications. The device captures and processes images locally in real-time, determines if hand-washing procedures have been correctly undertaken and then passes the resulting high-level data over a low-bandwidth wireless link. The paper outlines the hardware and software mechanisms of the VAMP system and illustrates that it offers an easy to integrate sensor solution to adequately monitor and improve hand hygiene quality. Future work to develop a miniaturized, low cost system capable of being integrated into everyday products is also discussed.

Miniaturised multi-MEMS sensor development

Complex systems, from environmental behaviour to electronics reliability, can now be monitored with Wireless Sensor Networks (WSN), where multiple environmental sensors are deployed in remote locations. This ensures aggregation and reading of data, at lower cost and lower power consumption. Because miniaturisation of the sensing system is hampered by the fact that discrete sensors and electronics consume board area, the development of MEMS sensors offers a promising solution. At Tyndall, the fabrication flow of multiple sensors has been made compatible with CMOS circuitry to further reduce size and cost. An ideal platform on which to host these MEMS environmental sensors is the Tyndall modular wireless mote. This paper describes the development and test of the latest sensors incorporating temperature, humidity, corrosion, and gas. It demonstrates their deployment on the Tyndall platform, allowing real-time readings, data aggregation and cross-correlation capabilities. It also presents the design of the next generation sensing platform using the novel 10mm wireless cube developed by Tyndall.

Design and implementation of the embedded capacitance layers for decoupling of wireless sensor nodes

In this paper, the embedded capacitance material (ECM) is fabricated between the power and ground layers of the wireless sensor nodes, forming an integrated capacitance to replace the large amount of decoupling capacitors on the board. The ECM material, whose dielectric constant is 16, has the same size of the wireless sensor nodes of 3cm*3cm, with a thickness of only 14μm. Though the capacitance of a single ECM layer being only around 8nF, there are two reasons the ECM layers can still replace the high frequency decoupling capacitors (100nF in our case) on the board. The first reason is: the parasitic inductance of the ECM layer is much lower than the surface mount capacitors'. A smaller capacitance value of the ECM layer could achieve the same resonant frequency of the surface mount decoupling capacitors. Simulation and measurement fit this assumption well. The second reason is: more than one layer of ECM material are utilized during the design step to get a parallel connection of the several ECM capacitance layers, finally leading to a larger value of the capacitance and smaller value of parasitic. Characterization of the ECM is carried out by the LCR meter. To evaluate the behaviors of the ECM layer, time and frequency domain measurements are performed on the power-bus decoupling of the wireless sensor nodes. Comparison with the measurements of bare PCB board and decoupling capacitors solution are provided to show the improvement of the ECM layer. Measurements show that the implementation of the ECM layer can not only save the space of the surface mount decoupling capacitors, but also provide better power-bus decoupling to the nodes.

GENESI: Wireless sensor networks for structural monitoring

The GENESI project has the ambitious goal of bringing WSN technology to the level where it can provide the core of the next generation of systems for structural health monitoring that are long lasting, pervasive and totally distributed and autonomous. This goal requires embracing engineering and scientific challenges never successfully tackled before. Sensor nodes will be redesigned to overcome their current limitations, especially concerning energy storage and provisioning (we need devices with virtually infinite lifetime) and resilience to faults and interferences (for reliability and robustness). New software and protocols will be defined to fully take advantage of the new hardware, providing new paradigms for cross-layer interaction at all layers of the protocol stack and satisfying the requirements of a new concept of Quality of Service (QoS) that is application-driven, truly reflecting the end user perspective and expectations. The GENESI project will develop long lasting sensor nodes by combining cutting edge technologies for energy generation from the environment (energy harvesting) and green energy supply (small form factor fuel cells); GENESI will define models for energy harvesting, energy conservation in super-capacitors and supplemental energy availability through fuel cells, in addition to the design of new algorithms and protocols for dynamic allocation of sensing and communication tasks to the sensors. The project team will design communication protocols for large scale heterogeneous wireless sensor/actuator networks with energy-harvesting capabilities and define distributed mechanisms for context assessment and situation awareness. This paper presents an analysis of the GENESI system requirements in order to achieve the ambitious goals of the project. Extending from the requirements presented, the emergent system specification is discussed with respect to the selection and integration of relevant system components.The resulting integrated system will be evaluated and characterised to ensure that it is capable of satisfying the functional requirements of the project

Energy storage systems for wave energy converters and microgrids

The thesis initially gives an overview of the wave industry and the current state of some of the leading technologies as well as the energy storage systems that are inherently part of the power take-off mechanism. The benefits of electrical energy storage systems for wave energy converters are then outlined as well as the key parameters required from them. The options for storage systems are investigated and the reasons for examining supercapacitors and lithium-ion batteries in more detail are shown. The thesis then focusses on a particular type of offshore wave energy converter in its analysis, the backward bent duct buoy employing a Wells turbine. Variable speed strategies from the research literature which make use of the energy stored in the turbine inertia are examined for this system, and based on this analysis an appropriate scheme is selected. A supercapacitor power smoothing approach is presented in conjunction with the variable speed strategy. As long component lifetime is a requirement for offshore wave energy converters, a computer-controlled test rig has been built to validate supercapacitor lifetimes to manufacturer’s specifications. The test rig is also utilised to determine the effect of temperature on supercapacitors, and determine application lifetime. Cycle testing is carried out on individual supercapacitors at room temperature, and also at rated temperature utilising a thermal chamber and equipment programmed through the general purpose interface bus by Matlab. Application testing is carried out using time-compressed scaled-power profiles from the model to allow a comparison of lifetime degradation. Further applications of supercapacitors in offshore wave energy converters are then explored. These include start-up of the non-self-starting Wells turbine, and low-voltage ride-through examined to the limits specified in the Irish grid code for wind turbines. These applications are investigated with a more complete model of the system that includes a detailed back-to-back converter coupling a permanent magnet synchronous generator to the grid. Supercapacitors have been utilised in combination with battery systems for many applications to aid with peak power requirements and have been shown to improve the performance of these energy storage systems. The design, implementation, and construction of coupling a 5 kW h lithium-ion battery to a microgrid are described. The high voltage battery employed a continuous power rating of 10 kW and was designed for the future EV market with a controller area network interface. This build gives a general insight to some of the engineering, planning, safety, and cost requirements of implementing a high power energy storage system near or on an offshore device for interface to a microgrid or grid.

Low power predictable memory and processing architectures

Great demand in power optimized devices shows promising economic potential and draws lots of attention in industry and research area. Due to the continuously shrinking CMOS process, not only dynamic power but also static power has emerged as a big concern in power reduction. Other than power optimization, average-case power estimation is quite significant for power budget allocation but also challenging in terms of time and effort. In this thesis, we will introduce a methodology to support modular quantitative analysis in order to estimate average power of circuits, on the basis of two concepts named Random Bag Preserving and Linear Compositionality. It can shorten simulation time and sustain high accuracy, resulting in increasing the feasibility of power estimation of big systems. For power saving, firstly, we take advantages of the low power characteristic of adiabatic logic and asynchronous logic to achieve ultra-low dynamic and static power. We will propose two memory cells, which could run in adiabatic and non-adiabatic mode. About 90% dynamic power can be saved in adiabatic mode when compared to other up-to-date designs. About 90% leakage power is saved. Secondly, a novel logic, named Asynchronous Charge Sharing Logic (ACSL), will be introduced. The realization of completion detection is simplified considerably. Not just the power reduction improvement, ACSL brings another promising feature in average power estimation called data-independency where this characteristic would make power estimation effortless and be meaningful for modular quantitative average case analysis. Finally, a new asynchronous Arithmetic Logic Unit (ALU) with a ripple carry adder implemented using the logically reversible/bidirectional characteristic exhibiting ultra-low power dissipation with sub-threshold region operating point will be presented. The proposed adder is able to operate multi-functionally.

Development of germanium/silicon integration for near infrared detection

Silicon (Si) is the base material for electronic technologies and is emerging as a very attractive platform for photonic integrated circuits (PICs). PICs allow optical systems to be made more compact with higher performance than discrete optical components. Applications for PICs are in the area of fibre-optic communication, biomedical devices, photovoltaics and imaging. Germanium (Ge), due to its suitable bandgap for telecommunications and its compatibility with Si technology is preferred over III-V compounds as an integrated on-chip detector at near infrared wavelengths. There are two main approaches for Ge/Si integration: through epitaxial growth and through direct wafer bonding. The lattice mismatch of ~4.2% between Ge and Si is the main problem of the former technique which leads to a high density of dislocations while the bond strength and conductivity of the interface are the main challenges of the latter. Both result in trap states which are expected to play a critical role. Understanding the physics of the interface is a key contribution of this thesis. This thesis investigates Ge/Si diodes using these two methods. The effects of interface traps on the static and dynamic performance of Ge/Si avalanche photodetectors have been modelled for the first time. The thesis outlines the original process development and characterization of mesa diodes which were fabricated by transferring a ~700 nm thick layer of p-type Ge onto n-type Si using direct wafer bonding and layer exfoliation. The effects of low temperature annealing on the device performance and on the conductivity of the interface have been investigated. It is shown that the diode ideality factor and the series resistance of the device are reduced after annealing. The carrier transport mechanism is shown to be dominated by generation–recombination before annealing and by direct tunnelling in forward bias and band-to-band tunnelling in reverse bias after annealing. The thesis presents a novel technique to realise photodetectors where one of the substrates is thinned by chemical mechanical polishing (CMP) after bonding the Si-Ge wafers. Based on this technique, Ge/Si detectors with remarkably high responsivities, in excess of 3.5 A/W at 1.55 μm at −2 V, under surface normal illumination have been measured. By performing electrical and optical measurements at various temperatures, the carrier transport through the hetero-interface is analysed by monitoring the Ge band bending from which a detailed band structure of the Ge/Si interface is proposed for the first time. The above unity responsivity of the detectors was explained by light induced potential barrier lowering at the interface. To our knowledge this is the first report of light-gated responsivity for vertically illuminated Ge/Si photodiodes. The wafer bonding approach followed by layer exfoliation or by CMP is a low temperature wafer scale process. In principle, the technique could be extended to other materials such as Ge on GaAs, or Ge on SOI. The unique results reported here are compatible with surface normal illumination and are capable of being integrated with CMOS electronics and readout units in the form of 2D arrays of detectors. One potential future application is a low-cost Si process-compatible near infrared camera.

Simulation of multigate SOI transistors with silicon, germanium and III-V channels

In this work by employing numerical three-dimensional simulations we study the electrical performance and short channel behavior of several multi-gate transistors based on advanced SOI technology. These include FinFETs, triple-gate and gate-all-around nanowire FETs with different channel material, namely Si, Ge, and III-V compound semiconductors, all most promising candidates for future nanoscale CMOS technologies. Also, a new type of transistor called “junctionless nanowire transistor” is presented and extensive simulations are carried out to study its electrical characteristics and compare with the conventional inversion- and accumulation-mode transistors. We study the influence of device properties such as different channel material and orientation, dimensions, and doping concentration as well as quantum effects on the performance of multi-gate SOI transistors. For the modeled n-channel nanowire devices we found that at very small cross sections the nanowires with silicon channel are more immune to short channel effects. Interestingly, the mobility of the channel material is not as significant in determining the device performance in ultrashort channels as other material properties such as the dielectric constant and the effective mass. Better electrostatic control is achieved in materials with smaller dielectric constant and smaller source-to-drain tunneling currents are observed in channels with higher transport effective mass. This explains our results on Si-based devices. In addition to using the commercial TCAD software (Silvaco and Synopsys TCAD), we have developed a three-dimensional Schrödinger-Poisson solver based on the non-equilibrium Green’s functions formalism and in the framework of effective mass approximation. This allows studying the influence of quantum effects on electrical performance of ultra-scaled devices. We have implemented different mode-space methodologies in our 3D quantum-mechanical simulator and moreover introduced a new method to deal with discontinuities in the device structures which is much faster than the coupled-mode-space approach.

First principles modelling of nucleation and growth during atomic layer deposition onto III-V substrates

Atomic layer deposition (ALD) is now used in semiconductor fabrication lines to deposit nanometre-thin oxide films, and has thus enabled the introduction of high-permittivity dielectrics into the CMOS gate stack. With interest increasing in transistors based on high mobility substrates, such as GaAs, we are investigating the surface treatments that may improve the interface characteristics. We focus on incubation periods of ALD processes on III-V substrates. We have applied first principles Density Functional Theory (DFT) to investigate detailed chemistry of these early stages of growth, specifically substrate and ALD precursor interaction. We have modelled the ‘clean-up’ effect by which organometallic precursors: trimethylaluminium (TMA) or hafnium and titanium amides clean arsenic oxides off the GaAs surface before ALD growth of dielectric commences and similar effect on Si3N4 substrate. Our simulations show that ‘clean-up’ of an oxide film strongly depends on precursor ligand, its affinity to the oxide and the redox character of the oxide. The predominant pathway for a metalloid oxide such as arsenic oxide is reduction, producing volatile molecules or gettering oxygen from less reducible oxides. An alternative pathway is non-redox ligand exchange, which allows non-reducible oxides (e.g. SiO2) to be cleaned-up. First principles study shows also that alkylamides are more susceptible to decomposition rather than migration on the oxide surface. This improved understanding of the chemical principles underlying ‘clean-up’ allows us to rationalize and predict which precursors will perform the reaction. The comparison is made between selection of metal chlorides, methyls and alkylamides precursors.

Energy storage: battery materials and architectures at the nanoscale

Enterprise Ireland (Project CFTD07325). European Commission (EU Framework 7 project Nanofunction, (Beyond CMOS Nanodevices for Adding Functionalities to CMOS) www.Nanofunction.eu EU ICT Network of Excellence, Grant No.257375)

Research and design of high-speed advanced analogue front-ends for fibre-optic transmission systems

In the last decade, we have witnessed the emergence of large, warehouse-scale data centres which have enabled new internet-based software applications such as cloud computing, search engines, social media, e-government etc. Such data centres consist of large collections of servers interconnected using short-reach (reach up to a few hundred meters) optical interconnect. Today, transceivers for these applications achieve up to 100Gb/s by multiplexing 10x 10Gb/s or 4x 25Gb/s channels. In the near future however, data centre operators have expressed a need for optical links which can support 400Gb/s up to 1Tb/s. The crucial challenge is to achieve this in the same footprint (same transceiver module) and with similar power consumption as today’s technology. Straightforward scaling of the currently used space or wavelength division multiplexing may be difficult to achieve: indeed a 1Tb/s transceiver would require integration of 40 VCSELs (vertical cavity surface emitting laser diode, widely used for short‐reach optical interconnect), 40 photodiodes and the electronics operating at 25Gb/s in the same module as today’s 100Gb/s transceiver. Pushing the bit rate on such links beyond today’s commercially available 100Gb/s/fibre will require new generations of VCSELs and their driver and receiver electronics. This work looks into a number of state‐of-the-art technologies and investigates their performance restraints and recommends different set of designs, specifically targeting multilevel modulation formats. Several methods to extend the bandwidth using deep submicron (65nm and 28nm) CMOS technology are explored in this work, while also maintaining a focus upon reducing power consumption and chip area. The techniques used were pre-emphasis in rising and falling edges of the signal and bandwidth extensions by inductive peaking and different local feedback techniques. These techniques have been applied to a transmitter and receiver developed for advanced modulation formats such as PAM-4 (4 level pulse amplitude modulation). Such modulation format can increase the throughput per individual channel, which helps to overcome the challenges mentioned above to realize 400Gb/s to 1Tb/s transceivers.