Formation of sub-7 nm feature size PS-b-P4VP block copolymer structures by solvent vapour process

The nanometer range structure produced by thin films of diblock copolymers makes them a great of interest as templates for the microelectronics industry. We investigated the effect of annealing solvents and/or mixture of the solvents in case of symmetric Poly (styrene-block-4vinylpyridine) (PS-b-P4VP) diblock copolymer to get the desired line patterns. In this paper, we used different molecular weights PS-b-P4VP to demonstrate the scalability of such high χ BCP system which requires precise fine-tuning of interfacial energies achieved by surface treatment and that improves the wetting property, ordering, and minimizes defect densities. Bare Silicon Substrates were also modified with polystyrene brush and ethylene glycol self-assembled monolayer in a simple quick reproducible way. Also, a novel and simple in situ hard mask technique was used to generate sub-7nm Iron oxide nanowires with a high aspect ratio on Silicon substrate, which can be used to develop silicon nanowires post pattern transfer.

Semiconductor nanowire fabrication via bottom-up & top-down paradigms

Semiconductor nanowires are pseudo 1-D structures where the magnitude of the semiconducting material is confined to a length of less than 100 nm in two dimensions. Semiconductor nanowires have a vast range of potential applications, including electronic (logic devices, diodes), photonic (laser, photodetector), biological (sensors, drug delivery), energy (batteries, solar cells, thermoelectric generators), and magnetic (spintronic, memory) devices. Semiconductor nanowires can be fabricated by a range of methods which can be categorised into one of two paradigms, bottom-up or top-down. Bottom-up processes can be defined as those where structures are assembled from their sub-components in an additive fashion. Top-down fabrication strategies use sculpting or etching to carve structures from a larger piece of material in a subtractive fashion. This seminar will detail a number of novel routes to fabricate semiconductor nanowires by both bottom-up and top-down paradigms. Firstly, a novel bottom-up route to fabricate Ge nanowires with controlled diameter distributions in the sub-20 nm regime will be described. This route details nanowire synthesis and diameter control in the absence of a foreign seed metal catalyst. Additionally a top-down route to nanowire array fabrication will be detailed outlining the importance of surface chemistry in high-resolution electron beam lithography (EBL) using hydrogen silsesquioxane (HSQ) on Ge and Bi2Se3 surfaces. Finally, a process will be described for the directed self-assembly of a diblock copolymer (PS-b-PDMS) using an EBL defined template. This section will also detail a route toward selective template sidewall wetting of either block in the PS-b-PDMS system, through tailored functionalisation of the template and substrate surfaces.

Study of the kinetics and mechanism of rapid self-assembly in block copolymer thin films during solvo-microwave annealing

Microwave annealing is an emerging technique for achieving ordered patterns of block copolymer films on substrates. Little is understood about the mechanisms of microphase separation during the microwave annealing process and how it promotes the microphase separation of the blocks. Here, we use controlled power microwave irradiation in the presence of tetrahydrofuran (THF) solvent, to achieve lateral microphase separation in high- lamellar-forming poly(styrene-b-lactic acid) PS-b-PLA. A highly ordered line pattern was formed within seconds on silicon, germanium and silicon on insulator (SOI) substrates. In-situ temperature measurement of the silicon substrate coupled to condition changes during "solvo-microwave" annealing allowed understanding of the processes to be attained. Our results suggest that the substrate has little effect on the ordering process and is essentially microwave transparent but rather, it is direct heating of the polar THF molecules that causes microphase separation. It is postulated that the rapid interaction of THF with microwaves and the resultant temperature increase to 55 degrees C within seconds causes an increase of the vapor pressure of the solvent from 19.8 to 70 kPa. This enriched vapor environment increases the plasticity of both PS and PLA chains and leads to the fast self-assembly kinetics. Comparing the patterns formed on silicon, germanium and silicon on insulator (SOI) and also an in situ temperature measurement of silicon in the oven confirms the significance of the solvent over the role of substrate heating during "solvo-microwave" annealing. Besides the short annealing time which has technological importance, the coherence length is on a micron scale and dewetting is not observed after annealing. The etched pattern (PLA was removed by an Ar/O-2 reactive ion etch) was transferred to the underlying silicon substrate fabricating sub-20 nm silicon nanowires over large areas demonstrating that the morphology is consistent both across and through the film.