Pitting and porous layer formation on n-InP anodes

Surface pitting occurs when InP electrodes are anodized in KOH electrolytes at concentrations in the range 2 - 5 mol dm-3. The process has been investigated using atomic force microscopy (AFM) and the results correlated with cross-sectional transmission electron microscopy (TEM) and electroanalytical measurements. AFM measurements show that pitting of the surface occurs and the density of pits is observed to increase with time under both potentiodynamic and potentiostatic conditions. This indicates a progressive pit nucleation process and implies that the development of porous domains beneath the surface is also progressive in nature. Evidence for this is seen in plan view TEM images in which individual domains are seen to be at different stages of development. Analysis of the cyclic voltammograms of InP electrodes in 5 mol dm-3 KOH indicates that, above a critical potential for pit formation, the anodic current is predominantly time dependent and there is little differential dependence of the current on potential. Thus, pores continue to grow with time when the potential is high enough to maintain depletion layer breakdown conditions.

Electrochemical pore formation on InP in alkaline solutions

The surface properties of InP electrodes were examined following anodization in (NH4)2S and KOH electrolytes. In both solutions, the observation of current peaks in the cyclic voltammetric curves was attributed to selective etching of the substrate and a film formation process. AFM images of samples anodized in the sulfide solution, revealed surface pitting and TEM micrographs revealed the porous nature of the film formed on top of the pitted substrate. After anodization in the KOH electrolyte, TEM images revealed that a porous layer extending 500 nm into the substrate had been formed. Analysis of the composition of the anodic products indicates the presence of In2S3 in films grown in (NH4)2S and an In2O3 phase within the porous network formed in KOH.

Effects of alternating current voltage amplitude and oxide capacitance on mid-gap interface state defect density extractions in In0.53Ga 0.47As capacitors

This work looks at the effect on mid-gap interface state defect density estimates for In0.53Ga0.47As semiconductor capacitors when different AC voltage amplitudes are selected for a fixed voltage bias step size (100 mV) during room temperature only electrical characterization. Results are presented for Au/Ni/Al2O3/In0.53Ga0.47As/InP metal–oxide–semiconductor capacitors with (1) n-type and p-type semiconductors, (2) different Al2O3 thicknesses, (3) different In0.53Ga0.47As surface passivation concentrations of ammonium sulphide, and (4) different transfer times to the atomic layer deposition chamber after passivation treatment on the semiconductor surface—thereby demonstrating a cross-section of device characteristics. The authors set out to determine the importance of the AC voltage amplitude selection on the interface state defect density extractions and whether this selection has a combined effect with the oxide capacitance. These capacitors are prototypical of the type of gate oxide material stacks that could form equivalent metal–oxide–semiconductor field-effect transistors beyond the 32 nm technology node. The authors do not attempt to achieve the best scaled equivalent oxide thickness in this work, as our focus is on accurately extracting device properties that will allow the investigation and reduction of interface state defect densities at the high-k/III–V semiconductor interface. The operating voltage for future devices will be reduced, potentially leading to an associated reduction in the AC voltage amplitude, which will force a decrease in the signal-to-noise ratio of electrical responses and could therefore result in less accurate impedance measurements. A concern thus arises regarding the accuracy of the electrical property extractions using such impedance measurements for future devices, particularly in relation to the mid-gap interface state defect density estimated from the conductance method and from the combined high–low frequency capacitance–voltage method. The authors apply a fixed voltage step of 100 mV for all voltage sweep measurements at each AC frequency. Each of these measurements is repeated 15 times for the equidistant AC voltage amplitudes between 10 mV and 150 mV. This provides the desired AC voltage amplitude to step size ratios from 1:10 to 3:2. Our results indicate that, although the selection of the oxide capacitance is important both to the success and accuracy of the extraction method, the mid-gap interface state defect density extractions are not overly sensitive to the AC voltage amplitude employed regardless of what oxide capacitance is used in the extractions, particularly in the range from 50% below the voltage sweep step size to 50% above it. Therefore, the use of larger AC voltage amplitudes in this range to achieve a better signal-to-noise ratio during impedance measurements for future low operating voltage devices will not distort the extracted interface state defect density.

Investigation of electrically active defects at the interface of high-k dielectrics and compound semiconductors

As silicon based devices in integrated circuits reach the fundamental limits of dimensional scaling there is growing research interest in the use of high electron mobility channel materials, such as indium gallium arsenide (InGaAs), in conjunction with high dielectric constant (high-k) gate oxides, for Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) based devices. The motivation for employing high mobility channel materials is to reduce power dissipation in integrated circuits while also providing improved performance. One of the primary challenges to date in the field of III-V semiconductors has been the observation of high levels of defect densities at the high-k/III-V interface, which prevents surface inversion of the semiconductor. The work presented in this PhD thesis details the characterization of MOS devices incorporating high-k dielectrics on III-V semiconductors. The analysis examines the effect of modifying the semiconductor bandgap in MOS structures incorporating InxGa1-xAs (x: 0, 0.15. 0.3, 0.53) layers, the optimization of device passivation procedures designed to reduce interface defect densities, and analysis of such electrically active interface defect states for the high-k/InGaAs system. Devices are characterized primarily through capacitance-voltage (CV) and conductance-voltage (GV) measurements of MOS structures both as a function of frequency and temperature. In particular, the density of electrically active interface states was reduced to the level which allowed the observation of true surface inversion behavior in the In0.53Ga0.47As MOS system. This was achieved by developing an optimized (NH4)2S passivation, minimized air exposure, and atomic layer deposition of an Al2O3 gate oxide. An extraction of activation energies allows discrimination of the mechanisms responsible for the inversion response. Finally a new approach is described to determine the minority carrier generation lifetime and the oxide capacitance in MOS structures. The method is demonstrated for an In0.53Ga0.47As system, but is generally applicable to any MOS structure exhibiting a minority carrier response in inversion.

Electron beam lithography assisted high-resolution pattern generation

This thesis details the top-down fabrication of nanostructures on Si and Ge substrates by electron beam lithography (EBL). Various polymeric resist materials were used to create nanopatterns by EBL and Chapter 1 discusses the development characteristics of these resists. Chapter 3 describes the processing parameters, resolution and topographical and structural changes of a new EBL resist known as ‘SML’. A comparison between SML and the standard resists PMMA and ZEP520A was undertaken to determine the suitability of SML as an EBL resist. It was established that SML is capable of high-resolution patterning and showed good pattern transfer capabilities. Germanium is a desirable material for use in microelectronic applications due to a number of superior qualities over silicon. EBL patterning of Ge with high-resolution hydrogen silsesquioxane (HSQ) resist is however difficult due to the presence of native surface oxides. Thus, to combat this problem a new technique for passivating Ge surfaces prior to EBL processes is detailed in Chapter 4. The surface passivation was carried out using simple acids like citric acid and acetic acid. The acids were gentle on the surface and enabled the formation of high-resolution arrays of Ge nanowires using HSQ resist. Chapter 5 details the directed self-assembly (DSA) of block copolymers (BCPs) on EBL patterned Si and, for the very first time, Ge surfaces. DSA of BCPs on template substrates is a promising technology for high volume and cost effective nanofabrication. The BCP employed for this study was poly (styrene-b-ethylene oxide) and the substrates were pre-defined by HSQ templates produced by EBL. The DSA technique resulted into pattern rectification (ordering in BCP) and in pattern multiplication within smaller areas.

Development of InAlN HEMTs for space application

This thesis investigates the emerging InAlN high electron mobility transistor (HEMT) technology with respect to its application in the space industry. The manufacturing processes and device performance of InAlN HEMTs were compared to AlGaN HEMTs, also produced as part of this work. RF gain up to 4 GHz was demonstrated in both InAlN and AlGaN HEMTs with gate lengths of 1 μm, with InAlN HEMTs generally showing higher channel currents (~150 c.f. 60 mA/mm) but also degraded leakage properties (~ 1 x 10-4 c.f. < 1 x 10-8 A/mm) with respect to AlGaN. An analysis of device reliability was undertaken using thermal stability, radiation hardness and off-state breakdown measurements. Both InAlN and AlGaN HEMTs showed excellent stability under space-like conditions, with electrical operation maintained after exposure to 9.2 Mrad of gamma radiation at a dose rate of 6.6 krad/hour over two months and after storage at 250°C for four weeks. Furthermore a link was established between the optimisation of device performance (RF gain, power handling capabilities and leakage properties) and reliability (radiation hardness, thermal stability and breakdown properties), particularly with respect to surface passivation. Following analysis of performance and reliability data, the InAlN HEMT device fabrication process was optimised by adjusting the metal Ohmic contact formation process (specifically metal stack thicknesses and anneal conditions) and surface passivation techniques (plasma power during dielectric layer deposition), based on an existing AlGaN HEMT process. This resulted in both a reduction of the contact resistivity to around 1 x 10-4 Ω.cm2 and the suppression of degrading trap-related effects, bringing the measured gate-lag close to zero. These discoveries fostered a greater understanding of the physical mechanisms involved in device operation and manufacture, which is elaborated upon in the final chapter.