Analog circuit synthesis performing fast Pareto frontier exploration and analysis through 3D graphs

This paper presents a technique for performing analog design synthesis at circuit level providing feedback to the designer through the exploration of the Pareto frontier. A modified simulated annealing which is able to perform crossover with past anchor points when a local minimum is found which is used as the optimization algorithm on the initial synthesis procedure. After all specifications are met, the algorithm searches for the extreme points of the Pareto frontier in order to obtain a non-exhaustive exploration of the Pareto front. Finally, multi-objective particle swarm optimization is used to spread the results and to find a more accurate frontier. Piecewise linear functions are used as single-objective cost functions to produce a smooth and equal convergence of all measurements to the desired specifications during the composition of the aggregate objective function. To verify the presented technique two circuits were designed, which are: a Miller amplifier with 96 dB Voltage gain, 15.48 MHz unity gain frequency, slew rate of 19.2 V/mu s with a current supply of 385.15 mu A, and a complementary folded cascode with 104.25 dB Voltage gain, 18.15 MHz of unity gain frequency and a slew rate of 13.370 MV/mu s. These circuits were synthesized using a 0.35 mu m technology. The results show that the method provides a fast approach for good solutions using the modified SA and further good Pareto front exploration through its connection to the particle swarm optimization algorithm.

A multi-objective adaptive immune algorithm for multi-application NoC mapping

Current SoC design trends are characterized by the integration of larger amount of IPs targeting a wide range of application fields. Such multi-application systems are constrained by a set of requirements. In such scenario network-on-chips (NoC) are becoming more important as the on-chip communication structure. Designing an optimal NoC for satisfying the requirements of each individual application requires the specification of a large set of configuration parameters leading to a wide solution space. It has been shown that IP mapping is one of the most critical parameters in NoC design, strongly influencing the SoC performance. IP mapping has been solved for single application systems using single and multi-objective optimization algorithms. In this paper we propose the use of a multi-objective adaptive immune algorithm (M(2)AIA), an evolutionary approach to solve the multi-application NoC mapping problem. Latency and power consumption were adopted as the target multi-objective functions. To compare the efficiency of our approach, our results are compared with those of the genetic and branch and bound multi-objective mapping algorithms. We tested 11 well-known benchmarks, including random and real applications, and combines up to 8 applications at the same SoC. The experimental results showed that the M(2)AIA decreases in average the power consumption and the latency 27.3 and 42.1 % compared to the branch and bound approach and 29.3 and 36.1 % over the genetic approach.

Six-element circuit for maximum power point tracking in photovoltaic-motor systems with variable-frequency drives

A low-cost circuit was developed for stable and efficient maximum power point (MPP) tracking in autonomous photo voltaic-motor systems with variable-frequency drives (VFDs). The circuit is made of two resistors, two capacitors, and two Zener diodes. Its input is the photovoltaic (PV) array voltage and its output feeds the proportional-integral-derivative (PID) controller usually integrated into, the drive. The steady-state frequency-voltage oscillations induced by the circuit were treated in a simplified mathematical model, which was validated by widely characterizing a PV-powered centrifugal pump. General procedures for circuit and controller tuning were recommended based on model equations. The tracking circuit presented here is widely applicable to PV-motor system with VFDs, offering an. efficient open-access technology of unique simplicity. Copyright (C) 2010 John Wiley & Sons, Ltd.

A Low Power CMOS Voltage Regulator for a Wireless Blood Pressure Biosensor

This paper describes a CMOS implementation of a linear voltage regulator (LVR) used to power up implanted physiological signal systems, as it is the case of a wireless blood pressure biosensor. The topology is based on a classical structure of a linear low-dropout regulator. The circuit is powered up from an RF link, thus characterizing a passive radio frequency identification (RFID) tag. The LVR was designed to meet important features such as low power consumption and small silicon area, without the need for any external discrete components. The low power operation represents an essential condition to avoid a high-energy RF link, thus minimizing the transmitted power and therefore minimizing the thermal effects on the patient's tissues. The project was implemented in a 0.35-mu m CMOS process, and the prototypes were tested to validate the overall performance. The LVR output is regulated at 1 V and supplies a maximum load current of 0.5 mA at 37 degrees C. The load regulation is 13 mV/mA, and the line regulation is 39 mV/V. The LVR total power consumption is 1.2 mW.

A complete CMOS UWB timed-array transmitter with a 3D Vivaldi antenna array for electronic high-resolution beam spatial scanning

We present a new Ultra Wide Band (UWB) Timed- Array Transmitter System with Beamforming capability for high-resolution remote acquisition of vital signals. The system consists of four identical channels, where each is formed of a serial topology with three modules: programmable delay circuit (PDC or τ), a novel UWB 5th Gaussian Derivative order pulse generator circuit (PG), and a planar Vivaldi antenna. The circuit was designed using 0.18μm CMOS standard process and the planar antenna array was designed with filmconductor on Rogers RO3206 substrate. Spice simulations results showed the pulse generation with 104 mVpp amplitude and 500 ps width. The power consumption is 543 μW, and energy consumption 0.27 pJ per pulse using a 2V power supply at a pulse repetition rate (PRR) of 100 MHz. Electromagnetic simulations results, using CST Microwave (MW) Studio 2011, showed the main lobe radiation with a gain maximum of 13.2 dB, 35.5º x 36.7º angular width, and a beam steering between 17º and -11º for azimuthal (θ) angles and 17º and -18º for elevation (φ) angles at the center frequency of 6 GHz