Sistematização da experiência da cooperapas: uma cooperativa de produtores agroecológicos de parelheiros, São Paulo/SP

A transição agroecológica, enquanto um processo de estímulo à adoção de práticas agrícolas sustentáveis implica na gradual construção do conhecimento agroecológico, por meio da troca de saberes, experiências e interpretação dos (as) agricultores (as) sobre os contextos em que vivem e produzem, configurando-se em um modo alternativo de produção, em contraponto ao modelo atual convencional. Novos caminhos que tragam a conservação da biodiversidade, a autorrealização individual e comunitária, e a autogestão política e econômica são prioritários e urgentes. A presente pesquisa teve por objetivo sistematizar a experiência de transição agroecológica da CooperAPAs, localizada em Parelheiros, zona sul do município de São Paulo, por meio da identificação de representações de agroecologia, relações saúde, ambiente e políticas públicas, bem como os principais interesses e dificuldades de agricultores e técnicos envolvidos em algum momento específico da trajetória de formação, implementação e/ou desenvolvimento da CooperAPAs. Foi utilizado o método de sistematização de experiências, tendo como instrumentos de pesquisa a análise documental, entrevistas e oficina de construção da linha do tempo. De modo geral, os participantes reconheciam impactos positivos e negativos de suas ações sobre a saúde e o ambiente. Dentre as necessidades identificadas, destacou-se maior sensibilização e empoderamento de todos os cooperados, para que possam contribuir mais ativamente no fortalecimento da cooperativa, a fim de garantir maior acesso às políticas públicas vigentes, ao mercado, e à comercialização, melhorando, consequentemente, condições socioambientais e econômicas destes agricultores. Para tal, recomenda-se a adoção, pela cooperativa, de estratégias socioeducativas participativas, como a Aprendizagem Social, que favoreçam o diálogo, a negociação de conflitos e a gestão compartilhada, como um novo caminho para a CooperAPAs.

Field and laboratory performance evaluation of a field-blended rubber asphalt.

ALICE is one of four major experiments of particle accelerator LHC installed in the European laboratory CERN. The management committee of the LHC accelerator has just approved a program update for this experiment. Among the upgrades planned for the coming years of the ALICE experiment is to improve the resolution and tracking efficiency maintaining the excellent particles identification ability, and to increase the read-out event rate to 100 KHz. In order to achieve this, it is necessary to update the Time Projection Chamber detector (TPC) and Muon tracking (MCH) detector modifying the read-out electronics, which is not suitable for this migration. To overcome this limitation the design, fabrication and experimental test of new ASIC named SAMPA has been proposed . This ASIC will support both positive and negative polarities, with 32 channels per chip and continuous data readout with smaller power consumption than the previous versions. This work aims to design, fabrication and experimental test of a readout front-end in 130nm CMOS technology with configurable polarity (positive/negative), peaking time and sensitivity. The new SAMPA ASIC can be used in both chambers (TPC and MCH). The proposed front-end is composed of a Charge Sensitive Amplifier (CSA) and a Semi-Gaussian shaper. In order to obtain an ASIC integrating 32 channels per chip, the design of the proposed front-end requires small area and low power consumption, but at the same time requires low noise. In this sense, a new Noise and PSRR (Power Supply Rejection Ratio) improvement technique for the CSA design without power and area impact is proposed in this work. The analysis and equations of the proposed circuit are presented which were verified by electrical simulations and experimental test of a produced chip with 5 channels of the designed front-end. The measured equivalent noise charge was <550e for 30mV/fC of sensitivity at a input capacitance of 18.5pF. The total core area of the front-end was 2300?m × 150?m, and the measured total power consumption was 9.1mW per channel.

Noise and PSRR improvement technique for TPC readout front-end in CMOS. technology.

ALICE is one of four major experiments of particle accelerator LHC installed in the European laboratory CERN. The management committee of the LHC accelerator has just approved a program update for this experiment. Among the upgrades planned for the coming years of the ALICE experiment is to improve the resolution and tracking efficiency maintaining the excellent particles identification ability, and to increase the read-out event rate to 100 KHz. In order to achieve this, it is necessary to update the Time Projection Chamber detector (TPC) and Muon tracking (MCH) detector modifying the read-out electronics, which is not suitable for this migration. To overcome this limitation the design, fabrication and experimental test of new ASIC named SAMPA has been proposed . This ASIC will support both positive and negative polarities, with 32 channels per chip and continuous data readout with smaller power consumption than the previous versions. This work aims to design, fabrication and experimental test of a readout front-end in 130nm CMOS technology with configurable polarity (positive/negative), peaking time and sensitivity. The new SAMPA ASIC can be used in both chambers (TPC and MCH). The proposed front-end is composed of a Charge Sensitive Amplifier (CSA) and a Semi-Gaussian shaper. In order to obtain an ASIC integrating 32 channels per chip, the design of the proposed front-end requires small area and low power consumption, but at the same time requires low noise. In this sense, a new Noise and PSRR (Power Supply Rejection Ratio) improvement technique for the CSA design without power and area impact is proposed in this work. The analysis and equations of the proposed circuit are presented which were verified by electrical simulations and experimental test of a produced chip with 5 channels of the designed front-end. The measured equivalent noise charge was <550e for 30mV/fC of sensitivity at a input capacitance of 18.5pF. The total core area of the front-end was 2300?m × 150?m, and the measured total power consumption was 9.1mW per channel.