Field and laboratory performance evaluation of a field-blended rubber asphalt.

ALICE is one of four major experiments of particle accelerator LHC installed in the European laboratory CERN. The management committee of the LHC accelerator has just approved a program update for this experiment. Among the upgrades planned for the coming years of the ALICE experiment is to improve the resolution and tracking efficiency maintaining the excellent particles identification ability, and to increase the read-out event rate to 100 KHz. In order to achieve this, it is necessary to update the Time Projection Chamber detector (TPC) and Muon tracking (MCH) detector modifying the read-out electronics, which is not suitable for this migration. To overcome this limitation the design, fabrication and experimental test of new ASIC named SAMPA has been proposed . This ASIC will support both positive and negative polarities, with 32 channels per chip and continuous data readout with smaller power consumption than the previous versions. This work aims to design, fabrication and experimental test of a readout front-end in 130nm CMOS technology with configurable polarity (positive/negative), peaking time and sensitivity. The new SAMPA ASIC can be used in both chambers (TPC and MCH). The proposed front-end is composed of a Charge Sensitive Amplifier (CSA) and a Semi-Gaussian shaper. In order to obtain an ASIC integrating 32 channels per chip, the design of the proposed front-end requires small area and low power consumption, but at the same time requires low noise. In this sense, a new Noise and PSRR (Power Supply Rejection Ratio) improvement technique for the CSA design without power and area impact is proposed in this work. The analysis and equations of the proposed circuit are presented which were verified by electrical simulations and experimental test of a produced chip with 5 channels of the designed front-end. The measured equivalent noise charge was <550e for 30mV/fC of sensitivity at a input capacitance of 18.5pF. The total core area of the front-end was 2300?m × 150?m, and the measured total power consumption was 9.1mW per channel.

Noise and PSRR improvement technique for TPC readout front-end in CMOS. technology.

ALICE is one of four major experiments of particle accelerator LHC installed in the European laboratory CERN. The management committee of the LHC accelerator has just approved a program update for this experiment. Among the upgrades planned for the coming years of the ALICE experiment is to improve the resolution and tracking efficiency maintaining the excellent particles identification ability, and to increase the read-out event rate to 100 KHz. In order to achieve this, it is necessary to update the Time Projection Chamber detector (TPC) and Muon tracking (MCH) detector modifying the read-out electronics, which is not suitable for this migration. To overcome this limitation the design, fabrication and experimental test of new ASIC named SAMPA has been proposed . This ASIC will support both positive and negative polarities, with 32 channels per chip and continuous data readout with smaller power consumption than the previous versions. This work aims to design, fabrication and experimental test of a readout front-end in 130nm CMOS technology with configurable polarity (positive/negative), peaking time and sensitivity. The new SAMPA ASIC can be used in both chambers (TPC and MCH). The proposed front-end is composed of a Charge Sensitive Amplifier (CSA) and a Semi-Gaussian shaper. In order to obtain an ASIC integrating 32 channels per chip, the design of the proposed front-end requires small area and low power consumption, but at the same time requires low noise. In this sense, a new Noise and PSRR (Power Supply Rejection Ratio) improvement technique for the CSA design without power and area impact is proposed in this work. The analysis and equations of the proposed circuit are presented which were verified by electrical simulations and experimental test of a produced chip with 5 channels of the designed front-end. The measured equivalent noise charge was <550e for 30mV/fC of sensitivity at a input capacitance of 18.5pF. The total core area of the front-end was 2300?m × 150?m, and the measured total power consumption was 9.1mW per channel.

Poder empresarial e cobertura de analistas financeiros

Este estudo buscou investigar duas relações de interesse: a relação entre poder e cobertura de analistas financeiros no mercado acionário brasileiro, e a relação entre poder e assimetria informacional neste mercado, nos períodos de 2000 a 2010. O objetivo desta pesquisa envolveu verificar se o poder empresarial aumenta a assimetria informacional decorrentes dos custos de agência envolvidos e possibilidade de expropriação de valor (Jensen & Meckling, 1976), ou diminui a assimetria, uma vez que administração da empresa não se sente vulnerável a demissões ou possíveis embaraços a sua atuação, e opta por não omitir informações aos stakeholders (Bertrand & Mullainathan, 2003). Ainda relacionado ao ambiente informacional impactado pelo poder empresarial, buscou-se verificar se os analistas financeiros acompanham empresas que apresentam uma maior assimetria informacional, e assim cumprindo sua função de monitoramento da gestão empresarial (Healy & Palepu, 2001), ou menor assimetria, em decorrência dos custos envolvidos em se obter informações privadas (Frankel, Kothari & Weber, 2006). Com o uso de proxies criadas pela análise fatorial para capturar as especificidades relacionadas a poder empresarial e assimetria informacional no ambiente empresarial brasileiro, foram observadas uma relação negativa entre cobertura de analistas financeiros e poder empresarial e uma relação positiva entre assimetria e poder empresarial. Pelas hipóteses esquematizadas por Jiraporn, Liu e Kim (2012), que abarcam todas as relações possíveis entre assimetria, poder empresarial e cobertura de analistas financeiros, os resultados se enquadram na Hipótese da Opacidade.