143 resultados para Inverter multilivello ,Modulatori PWM ,Motore-asincrono ,Trifase ,Ponte-IGBT


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Electromagnetic compatibility of power electronic systems becomes an engineering discipline and it should be considered at the beginning stage of a design. Thus, a power electronics design becomes more complex and challenging and it requires a good communication between EMI and Power electronics experts. Three major issues in designing a power electronic system are Losses, EMI and Harmonics. These issues affect system cost, size, efficiency and quality and it is a tradeoff between these factors when we design a power converter.

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Multilevel inverters provide an attractive solution for power electronics when both reduced harmonic contents and high voltages are required. In this paper, a novel predictive current control technique is proposed for a three-phase multilevel inverter, which controls the capacitors voltages and load currents with low switching losses. The advantage of this contribution is that the technique can be applied to more voltage levels without significantly changing the control circuit. The three-phase three-level inverter with a pure inductive load has been implemented to track reference currents using analogue circuits and programmable logic device.

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This paper presents a new DC-DC Multi-Output Boost (MOB) converter which can share its total output between different series of output voltages for low and high power applications. This configuration can be utilised instead of several single output power supplies. This is a compatible topology for a diode-clamed inverter in the grid connection systems, where boosting low rectified output-voltage and series DC link capacitors is required. To verify the proposed topology, steady state and dynamic analysis of a MOB converter are examined. A simple control strategy has been proposed to demonstrate the performance of the proposed topology for a double-output boost converter. The topology and its control strategy can easily be extended to offer multiple outputs. Simulation and experimental results are presented to show the validity of the control strategy for the proposed converter.

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Objective: To determine whether differences existed in lower-extremity joint biomechanics during self-selected walking cadence (SW) and fast walking cadence (FW) in overweight- and normal-weight children.---------- Design: Survey.---------- Setting: Institutional gait study center.---------- Participants: Participants (N=20; mean age ± SD, 10.4±1.6y) from referred and volunteer samples were classified based on body mass index percentiles and stratified by age and sex. Exclusion criteria were a history of diabetes, neuromuscular disorder, or recent lower-extremity injury.---------- Main Outcome Measures: Sagittal, frontal, and transverse plane angular displacements (degrees) and peak moments (newton meters) at the hip, knee, and ankle joints.---------- Results: The level of significance was set at P less than .008. Compared with normal-weight children, overweight children had greater absolute peak joint moments at the hip (flexor, extensor, abductor, external rotator), the knee (flexor, extensor, abductor, adductor, internal rotator), and the ankle (plantarflexor, inverter, external/internal rotators). After including body weight as a covariate, overweight children had greater peak ankle dorsiflexor moments than normal-weight children. No kinematic differences existed between groups. Greater peak hip extensor moments and less peak ankle inverter moments occurred during FW than SW. There was greater angular displacement during hip flexion as well as less angular displacement at the hip (extension, abduction), knee (flexion, extension), and ankle (plantarflexion, inversion) during FW than SW.---------- Conclusions: Overweight children experienced increased joint moments, which can have long-term orthopedic implications and suggest a need for more nonweight-bearing activities within exercise prescription. The percent of increase in joint moments from SW to FW was not different for overweight and normal-weight children. These findings can be used in developing an exercise prescription that must involve weight-bearing activity.

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Objectives: To explore whether people's organ donation consent decisions occur via a reasoned and/or social reaction pathway. --------- Design: We examined prospectively students' and community members' decisions to register consent on a donor register and discuss organ donation wishes with family. --------- Method: Participants completed items assessing theory of planned behaviour (TPB; attitude, subjective norm, perceived behavioural control (PBC)), prototype/willingness model (PWM; donor prototype favourability/similarity, past behaviour), and proposed additional influences (moral norm, self-identity, recipient prototypes) for registering (N=339) and discussing (N=315) intentions/willingness. Participants self-reported their registering (N=177) and discussing (N=166) behaviour 1 month later. The utility of the (1) TPB, (2) PWM, (3) augmented TPB with PWM, and (4) augmented TPB with PWM and extensions was tested using structural equation modelling for registering and discussing intentions/willingness, and logistic regression for behaviour. --------- Results: While the TPB proved a more parsimonious model, fit indices suggested that the other proposed models offered viable options, explaining greater variance in communication intentions/willingness. The TPB, augmented TPB with PWM, and extended augmented TPB with PWM best explained registering and discussing decisions. The proposed and revised PWM also proved an adequate fit for discussing decisions. Respondents with stronger intentions (and PBC for registering) had a higher likelihood of registering and discussing. --------- Conclusions: People's decisions to communicate donation wishes may be better explained via a reasoned pathway (especially for registering); however, discussing involves more reactive elements. The role of moral norm, self-identity, and prototypes as influences predicting communication decisions were highlighted also.

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This thesis reports on the investigations, simulations and analyses of novel power electronics topologies and control strategies. The research is financed by an Australian Research Council (ARC) Linkage (07-09) grant. Therefore, in addition to developing original research and contributing to the available knowledge of power electronics, it also contributes to the design of a DC-DC converter for specific application to the auxiliary power supply in electric trains. Specifically, in this regard, it contributes to the design of a 7.5 kW DC-DC converter for the industrial partner (Schaffler and Associates Ltd) who supported this project. As the thesis is formatted as a ‘thesis by publication’, the contents are organized around published papers. The research has resulted in eleven papers, including seven peer reviewed and published conference papers, one published journal paper, two journal papers accepted for publication and one submitted journal paper (provisionally accepted subject to few changes). In this research, several novel DC-DC converter topologies are introduced, analysed, and tested. The similarity of all of the topologies devised lies in their ‘current circulating’ switching state, which allows them to store some energy in the inductor, as extra inductor current. The stored energy may be applied to enhance the performance of the converter in the occurrence of load current or input voltage disturbances. In addition, when there is an alternating load current, the ability to store energy allows the converter to perform satisfactorily despite frequently and highly varying load current. In this research, the capability of current storage has been utilised to design topologies for specific applications, and the enhancement of the performance of the considered applications has been illustrated. The simplest DC-DC converter topology, which has a ‘current circulating’ switching state, is the Positive Buck-Boost (PBB) converter (also known as the non-inverting Buck-Boost converter). Usually, the topology of the PBB converter is operating as a Buck or a Boost converter in applications with widely varying input voltage or output reference voltage. For example, in electric railways (the application of our industrial partner), the overhead line voltage alternates from 1000VDC to 500VDC and the required regulated voltage is 600VDC. In the course of this research, our industrial partner (Schaffler and Associates Ltd) industrialized a PBB converter–the ‘Mudo converter’–operating at 7.5 kW. Programming the onboard DSP and testing the PBB converter in experimental and nominal power and voltage was part of this research program. In the earlier stages of this research, the advantages and drawbacks of utilization of the ‘current circulating’ switching state in the positive Buck-Boost converter were investigated. In brief, the advantages were found to be robustness against input voltage and current load disturbances, and the drawback was extra conduction and switching loss. Although the robustness against disturbances is desirable for many applications, the price of energy loss must be minimized to attract attention to the utilization of the PBB converter. In further stages of this research, two novel control strategies for different applications were devised to minimise the extra energy loss while the advantages of the positive Buck-Boost converter were fully utilized. The first strategy is Smart Load Controller (SLC) for applications with pre-knowledge or predictability of input voltage and/or load current disturbances. A convenient example of these applications is electric/hybrid cars where a master controller commands all changes in loads and voltage sources. Therefore, the master controller has a pre-knowledge of the load and input voltage disturbances so it can apply the SLC strategy to utilize robustness of the PBB converter. Another strategy aiming to minimise energy loss and maximise the robustness in the face of disturbance is developed to cover applications with unexpected disturbances. This strategy is named Dynamic Hysteresis Band (DHB), and is used to manipulate the hysteresis band height after occurrence of disturbance to reduce dynamics of the output voltage. When no disturbance has occurred, the PBB converter works with minimum inductor current and minimum energy loss. New topologies based on the PBB converter have been introduced to address input voltage disturbances for different onboard applications. The research shows that the performance of applications of symmetrical/asymmetrical multi-level diode-clamped inverters, DC-networks, and linear-assisted RF amplifiers may be enhanced by the utilization of topologies based on the PBB converter. Multi-level diode-clamped inverters have the problem of DC-link voltage balancing when the power factor of their load closes to unity. This research has shown that this problem may be solved with a suitable multi-output DC-DC converter supplying DClink capacitors. Furthermore, the multi-level diode-clamped inverters supplied with asymmetrical DC-link voltages may improve the quality of load voltage and reduce the level of Electromagnetic Interference (EMI). Mathematical analyses and experiments on supplying symmetrical and asymmetrical multi-level inverters by specifically designed multi-output DC-DC converters have been reported in two journal papers. Another application in which the system performance can be improved by utilization of the ‘current circulating’ switching state is linear-assisted RF amplifiers in communicational receivers. The concept of ‘linear-assisted’ is to divide the signal into two frequency domains: low frequency, which should be amplified by a switching circuit; and the high frequency domain, which should be amplified by a linear amplifier. The objective is to minimize the overall power loss. This research suggests using the current storage capacity of a PBB based converter to increase its bandwidth, and to increase the domain of the switching converter. The PBB converter addresses the industrial demand for a DC-DC converter for the application of auxiliary power supply of a typical electric train. However, after testing the industrial prototype of the PBB converter, there were some voltage and current spikes because of switching. To attenuate this problem without significantly increasing the switching loss, the idea of Active Gate Signalling (AGS) is presented. AGS suggests a smart gate driver that selectively controls the switching process to reduce voltage/current spikes, without unacceptable reduction in the efficiency of switching.

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In recent years, multilevel converters are becoming more popular and attractive than traditional converters in high voltage and high power applications. Multilevel converters are particularly suitable for harmonic reduction in high power applications where semiconductor devices are not able to operate at high switching frequencies or in high voltage applications where multilevel converters reduce the need to connect devices in series to achieve high switch voltage ratings. This thesis investigated two aspects of multilevel converters: structure and control. The first part of this thesis focuses on inductance between a DC supply and inverter components in order to minimise loop inductance, which causes overvoltages and stored energy losses during switching. Three dimensional finite element simulations and experimental tests have been carried out for all sections to verify theoretical developments. The major contributions of this section of the thesis are as follows: The use of a large area thin conductor sheet with a rectangular cross section separated by dielectric sheets (planar busbar) instead of circular cross section wires, contributes to a reduction of the stray inductance. A number of approximate equations exist for calculating the inductance of a rectangular conductor but an assumption was made that the current density was uniform throughout the conductors. This assumption is not valid for an inverter with a point injection of current. A mathematical analysis of a planar bus bar has been performed at low and high frequencies and the inductance and the resistance values between the two points of the planar busbar have been determined. A new physical structure for a voltage source inverter with symmetrical planar bus bar structure called Reduced Layer Planar Bus bar, is proposed in this thesis based on the current point injection theory. This new type of planar busbar minimises the variation in stray inductance for different switching states. The reduced layer planar busbar is a new innovation in planar busbars for high power inverters with minimum separation between busbars, optimum stray inductance and improved thermal performances. This type of the planar busbar is suitable for high power inverters, where the voltage source is supported by several capacitors in parallel in order to provide a low ripple DC voltage during operation. A two layer planar busbar with different materials has been analysed theoretically in order to determine the resistance of bus bars during switching. Increasing the resistance of the planar busbar can gain a damping ratio between stray inductance and capacitance and affects the performance of current loop during switching. The aim of this section is to increase the resistance of the planar bus bar at high frequencies (during switching) and without significantly increasing the planar busbar resistance at low frequency (50 Hz) using the skin effect. This contribution shows a novel structure of busbar suitable for high power applications where high resistance is required at switching times. In multilevel converters there are different loop inductances between busbars and power switches associated with different switching states. The aim of this research is to consider all combinations of the switching states for each multilevel converter topology and identify the loop inductance for each switching state. Results show that the physical layout of the busbars is very important for minimisation of the loop inductance at each switch state. Novel symmetrical busbar structures are proposed for multilevel converters with diode-clamp and flying-capacitor topologies which minimise the worst case in stray inductance for different switching states. Overshoot voltages and thermal problems are considered for each topology to optimise the planar busbar structure. In the second part of the thesis, closed loop current techniques have been investigated for single and three phase multilevel converters. The aims of this section are to investigate and propose suitable current controllers such as hysteresis and predictive techniques for multilevel converters with low harmonic distortion and switching losses. This section of the thesis can be classified into three parts as follows: An optimum space vector modulation technique for a three-phase voltage source inverter based on a minimum-loss strategy is proposed. One of the degrees of freedom for optimisation of the space vector modulation is the selection of the zero vectors in the switching sequence. This new method improves switching transitions per cycle for a given level of distortion as the zero vector does not alternate between each sector. The harmonic spectrum and weighted total harmonic distortion for these strategies are compared and results show up to 7% weighted total harmonic distortion improvement over the previous minimum-loss strategy. The concept of SVM technique is a very convenient representation of a set of three-phase voltages or currents used for current control techniques. A new hysteresis current control technique for a single-phase multilevel converter with flying-capacitor topology is developed. This technique is based on magnitude and time errors to optimise the level change of converter output voltage. This method also considers how to improve unbalanced voltages of capacitors using voltage vectors in order to minimise switching losses. Logic controls require handling a large number of switches and a Programmable Logic Device (PLD) is a natural implementation for state transition description. The simulation and experimental results describe and verify the current control technique for the converter. A novel predictive current control technique is proposed for a three-phase multilevel converter, which controls the capacitors' voltage and load current with minimum current ripple and switching losses. The advantage of this contribution is that the technique can be applied to more voltage levels without significantly changing the control circuit. The three-phase five-level inverter with a pure inductive load has been implemented to track three-phase reference currents using analogue circuits and a programmable logic device.

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The paper discusses the operating principles and control characteristics of a dynamic voltage restorer (DVR). It is assumed that the source voltages contain interharmonic components in addition to fundamental components. The main aim of the DVR is to produce a set of clean balanced sinusoidal voltages across the load terminals irrespective of unbalance, distortion and voltage sag/swell in the supply voltage. An algorithm has been discussed for extracting fundamental phasor sequence components from the samples of three-phase voltages or current waveforms having integer harmonics and interharmonics. The DVR operation based on extracted components is demonstrated. The switching signal is generated using a deadbeat controller. It has been shown that the DVR is able to compensate these interharmonic components such that the load voltages are perfectly regulated. The DVR operation under deep voltage sag is also discussed. The proposed DVR operation is verified through the computer simulation studies using the MATLAB software package.

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In this paper, a static synchronous series compensator (SSSC), along with a fixed capacitor, is used to avoid torsional mode instability in a series compensated transmission system. A 48-step harmonic neutralized inverter is used for the realization of the SSSC. The system under consideration is the IEEE first benchmark model on SSR analysis. The system stability is studied both through eigenvalue analysis and EMTDC/PSCAD simulation studies. It is shown that the combination of the SSSC and the fixed capacitor improves the synchronizing power coefficient. The presence of the fixed capacitor ensures increased damping of small signal oscillations. At higher levels of fixed capacitor compensation, a damping controller is required to stabilize the torsional modes of SSR.

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The paper discusses the operating principles and control characteristics of a dynamic voltage restorer (DVR) that protects sensitive but unbalanced and/or distorted loads. The main aim of the DVR is to regulate the voltage at the load terminal irrespective of sag/swell, distortion, or unbalance in the supply voltage. In this paper, the DVR is operated in such a fashion that it does not supply or absorb any active power during the steady-state operation. Hence, a DC capacitor rather than a DC source can supply the voltage source inverter realizing the DVR. The proposed DVR operation is verified through extensive digital computer simulation studies.

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This paper investigates the control of a HVDC link, fed from an AC source through a controlled rectifier and feeding an AC line through a controlled inverter. The overall objective is to maintain maximum possible link voltage at the inverter while regulating the link current. In this paper the practical feedback design issues are investigated with a view of obtaining simple, robust designs that are easy to evaluate for safety and operability. The investigations are applicable to back-to-back links used for frequency decoupling and to long DC lines. The design issues discussed include: (i) a review of overall system dynamics to establish the time scale of different feedback loops and to highlight feedback design issues; (ii) the concept of using the inverter firing angle control to regulate link current when the rectifier firing angle controller saturates; and (iii) the design issues for the individual controllers including robust design for varying line conditions and the trade-off between controller complexity and the reduction of nonlinearity and disturbance effects

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The design and implementation of a high-power (2 MW peak) vector control drive is described. The inverter switching frequency is low, resulting in high-harmonic-content current waveforms. A block diagram of the physical system is given, and each component is described in some detail. The problem of commanded slip noise sensitivity, inherent in high-power vector control drives, is discussed, and a solution is proposed. Results are given which demonstrate the successful functioning of the system