A high cell count cascade full bridge converter for wide bandwidth ultrasonic transducer excitation

A nine level modular multilevel cascade converter (MMCC) based on four full bridge cells is shown driving a piezoelectric ultrasonic transducer at 71 and 39 kHz, in simulation and experimentally. The modular cells are small stackable PCBs, each with two fully integrated surface mount 22 V, 40 A MOSFET half-bridge converters, and include all control signal and power isolation. In this work, the bridges operate at 12 V and 384 kHz, to deliver a 96 Vpp 9 level waveform with an effective switching frequency of 3 MHz. A 9 pH air cored inductor forms a low pass filter in conjunction with the 3000 pF capacitance of the transducer load. Eight equally phase-displaced naturally sampled pulse width modulation (PWM) drive signals, along with the modulating sinusoid, are generated using phase accumulation techniques in a dedicated FPGA. Experimental time domain and FFT plots of the multilevel and transducer output waveforms are presented and discussed.

A hybrid cascaded multilevel inverter with supercapacitor direct integration for wind power systems

This paper presents a grid-side inverter based supercapacitor direct integration scheme for wind power systems. The inverter used in this study consists of a conventional two-level inverter and three H-bridge modules. Three supercapacitor banks are directly connected to the dc-links of H-bridge modules. This approach eliminates the need for interfacing dc-dc converters and thus considerably improves the overall efficiency. However, for the maximum utilization of super capacitors their voltages should be allowed to vary. As a result of this variable voltage space vectors of the hybrid inverter get distributed unevenly. To handle this issue, a modified PWM method and a space vector modulation method are proposed and they can generate undistorted current even in the presence of unevenly distributed space vectors. A supercapacitor voltage balancing method is also presented in this paper. Simulation results are presented to validate the efficacy of the proposed scheme, modulation methods and control techniques.

A new method of interfacing battery/supercapacitor energy storage systems for distributed energy sources

Battery-supercapacitor hybrid energy storage systems can achieve better power and energy performances compared to their individual use. These hybrid systems require separate dc-dc converters, or at least one dc-dc converter for the supercapacitor bank, to connect them to the dc-link of the grid connecting inverter. However, the use of such dc-dc converters introduces additional cost and power losses. Therefore, the possibility of direct connection of energy storage systems, to the dc-link of a diode clamped 3-level inverter is investigated in this paper. Even though the proposed topology does not use dc-dc converters, a vector selection method is proposed to produce a similar control flexibility that is found in the separate dc-dc converter topology. The major issue with the proposed system is the imminent imbalance of the neutral point potential. A PWM technique with modified carriers is used to solve this problem. Simulations are carried out using MATLAB/SIMULINK to verify the efficacy of the proposed system.

On the design of power buffer and its applications

A power electronics-based buffer is examined in which through control of its PWM converters, the buffer-load combination is driven to operate under either constant power or constant impedance modes. A battery, incorporated within the buffer, provides the energy storage facility to facilitate the necessary power flow control. Real power demand from upstream supply is regulated under fault condition, and the possibility of voltage or network instability is reduced. The proposed buffer is also applied to a wind farm. It is shown that the buffer stabilizes the power contribution from the farm. Based on a battery cost-benefit analysis, a method is developed to determine the optimal level of the power supplied from the wind farm and the corresponding capacity of the battery storage system.

Double star chopper cell converter for battery electric vehicles with inter-module SoC balancing and fault tolerant control

A modularized battery system with Double Star Chopper Cell (DSCC) based modular multilevel converter is proposed for a battery operated electric vehicle (EV). A design concept for the modularized battery micro-packs for DSCC is described. Multidimensional pulse width modulation (MD-PWM) with integrated inter-module SoC balancing and fault tolerant control is proposed and explained. The DSCC can be operated either as an inverter to drive the EV motor or as a synchronous rectifier connected to external three phase power supply equipment for charging the battery micro-packs. The methods of operation as inverter and synchronous rectifier with integrated inter-module SoC balancing and fault tolerant control are discussed. The proposed system operation as inverter and synchronous rectifier are verified through simulations and the results are presented.

HFL PV micro-inverter with front-end current-fed converter and half-wave cycloconverter

A high-frequency-link micro inverter is proposed with a front-end dual inductor push-pull converter and a grid-connected half-wave cycloconverter. Pulse width modulation is used to control the front-end converter and phase shift modulation is used at the back-end converter to obtain grid synchronized output current. A series resonant circuit and high-frequency transformer are used to interface the front-end and the back-end converters. The operation of the proposed micro-inverter in grid-connected mode is validated using MATLAB/Simpower simulation. Experimental results are provided to further validate the operation.

Switching period randomisation for multilevel converter modulation

The spectral energy associated with the carrier and sidebands of naturally sampled carrier based PWM can be spread by randomising the carrier (switch) half-period Tc = 1/2fc. So long as the switch duty cycle each period still correctly reflects the value of the modulating fundamental waveform as sampled during that switch period, then the fundamental component will remain undistorted. Natural sampling will ensure this occurs. Carrier based PWM can be extended to (m+1) level multilevel converter waveform generation by creating m triangular carriers, each with an equal 2*pi/m phase displacement. Alternatively the carrier disposition strategy calls for m amplitude displaced triangular carriers, each of amplitude 1/m and frequency mfc. Randomising these carrier sub-periods T0> = 1/2mfc is shown to generate (m+ 1) level PWM waveforms where the first (m-1) carrier groups are cancelled, while the remaining carrier and sidebands at multiples of mfc are spectrally spread. Numerous five level simulation and experimentally gathered randomised PWM waveforms are presented, showing the effects of the variation of the degree of randomisation, modulation depth and pulse number.

Phase accumulated carrier pulse width modulation

An alternative approach to digital PWM generation uses an accumulator rather than a counter to generate the carrier. This offers several advantages. The resolution and gain of the pulse width modulator remain constant regardless of the module clock frequency and PWM output frequency. The PWM resolution also becomes fixed at the register width. Even at high PWM frequencies, the resolution remains high when averaged over a number of PWM cycles. An inherent dithering of the PWM waveform introduced over successive cycles blurs the switching spectra without distorting the modulating waveform. The technique also lends itself to easily generating several phase shifted PWM waveforms suitable for multilevel converter modulation. Several example waveforms generated using both simulation and FPGA hardware are presented.