Third harmonic generation of the surface wave in the semiconductor-metal slowing-down structure

A nonlinear process is considered of the surface wave third harmonics generation in a slowing-down semiconductor-metal structure. The process is conditioned by non-parabolicity of the charge carrier dispersion law. It is shown that in narrow-gap semiconducting materials it is necessary to account for the process together with the surface wave second harmonics generation conditioned by nonlinearity of quasi-hydrodynamics and the Maxwell equations. The conclusion is made that the third harmonies amplitude in narrow-gap semiconductors may exceed substantially the signal amplitude at the 3w frequency in a gas plasma and be of the same order with the surface waves second harmonies amplitude.

Effect of heating nonlinearity on propagation of high-frequency surface waves at the semiconductor-metal interface

In approximation of weak heating influence of electron heating in the high-frequency surface wave field on propagation of surface wave (heating nonlinearity) is considered. It is shown that high-frequency surface wave propagates in direction perpendicular to the external magnetic field at the semiconductor-metal interface. A nonlinear dispersion equation is obtained and studied that allows to make conclusions about the contribution of heating nonlinearity to nonlinear process of considered interaction.

Resonant second harmonics generation of the submillimeter surface wave in the semiconductor superlattice bounded by a metal

In this study, the process of the resonant second harmonics generation of the submillimeter (SM), which is of interest for design of the semiconductor frequency multipliers is evaluated. Particularly, the possibility to use the semiconductor superlattice-metal structures as an effective second harmonics generator is demonstrated.

Two-channel waveguide modulator based on surface wave propagating in a semiconductor-metal thin-film structure

The results of theoretical investigations of two-channel waveguide modulator based on Surface Wave (SW) propagation are presented. The structure studied consists of two n-type semiconductor waveguide channels separated from each other by a dielectric gap and coated by a metal. The SW propagates at the semiconductor-metal interface across an external magnetic field which is parallel to the interface. An external dc voltage is applied to the metal surface of one channel to provide a small phase shift between two propagating modes. In a coupled mode approximation, two possible regimes of operation of the structure, namely as a directional coupler and as an electro-optical modulator, are considered. Our results suggest new applications in millimeter and submillimeter wave solid-state electronics and integrated optics.

Colloidal semiconductor nanocrystals : controlled synthesis and surface chemistry in organic media

Colloidal semiconductor nanocrystals (CS-NCs) possess compelling benefits of low-cost, large-scale solution processing, and tunable optoelectronic properties through controlled synthesis and surface chemistry engineering. These merits make them promising candidates for a variety of applications. This review focuses on the general strategies and recent developments of the controlled synthesis of CS-NCs in terms of crystalline structure, particle size, dominant exposed facet, and their surface passivation. Highlighted are the organic-media based synthesis of metal chalcogenide (including cadmium, lead, and copper chalcogenide) and metal oxide (including titanium oxide and zinc oxide) nanocrystals. Current challenges and thus future opportunities are also pointed out in this review.

High mobility diketopyrrolopyrrole (DPP)-based organic semiconductor materials for organic thin film transistors and photovoltaics

In recent years, the electron-accepting diketopyrrolopyrrole (DPP) moiety has been receiving considerable attention for constructing donor-acceptor (D-A) type organic semiconductors for a variety of applications, particularly for organic thin film transistors (OTFTs) and organic photovoltaics (OPVs). Through association of the DPP unit with appropriate electron donating building blocks, the resulting D-A molecules interact strongly in the solid state through intermolecular D-A and π-π interactions, leading to highly ordered structures at the molecular and microscopic levels. The closely packed molecules and crystalline domains are beneficial for intermolecular and interdomain (or intergranular) charge transport. Furthermore, the energy levels can be readily adjusted, affording p-type, n-type, or ambipolar organic semiconductors with highly efficient charge transport properties in OTFTs. In the past few years, a number of DPP-based small molecular and polymeric semiconductors have been reported to show mobility close to or greater than 1 cm2 V -1 s-1. DPP-based polymer semiconductors have achieved record high mobility values for p-type (hole mobility: 10.5 cm2 V-1 s-1), n-type (electron mobility: 3 cm2 V-1 s-1), and ambipolar (hole/electron mobilities: 1.18/1.86 cm2 V-1 s-1) OTFTs among the known polymer semiconductors. Many DPP-based organic semiconductors have favourable energy levels and band gaps along with high hole mobility, which enable them as promising donor materials for OPVs. Power conversion efficiencies (PCE) of up to 6.05% were achieved for OPVs using DPP-based polymers, demonstrating their potential usefulness for the organic solar cell technology. This article provides an overview of the recent exciting progress made in DPP-containing polymers and small molecules that have shown high charge carrier mobility, around 0.1 cm2 V-1 s-1 or greater. It focuses on the structural design, optoelectronic properties, molecular organization, morphology, as well as performances in OTFTs and OPVs of these high mobility DPP-based materials.

Poly(2,5-bis(2-octyldodecyl)-3,6-di(furan-2-yl)-2,5-dihydro-pyrrolo[3,4-c] pyrrole-1,4-dione-co-thieno[3,2-b]thiophene): A high performance polymer semiconductor for both organic thin film transistors and organic photovoltaics

A new diketopyrrolopyrrole (DPP)-containing donor-acceptor polymer, poly(2,5-bis(2-octyldodecyl)-3,6-di(furan-2-yl)-2,5-dihydro-pyrrolo[3,4-c] pyrrole-1,4-dione-co-thieno[3,2-b]thiophene) (PDBF-co-TT), is synthesized and studied as a semiconductor in organic thin film transistors (OTFTs) and organic photovoltaics (OPVs). High hole mobility of up to 0.53 cm 2 V -1 s -1 in bottom-gate, top-contact OTFT devices is achieved owing to the ordered polymer chain packing and favoured chain orientation, strong intermolecular interactions, as well as uniform film morphology of PDBF-co-TT. The optimum band gap of 1.39 eV and high hole mobility make this polymer a promising donor semiconductor for the solar cell application. When paired with a fullerene acceptor, PC 71BM, the resulting OPV devices show a high power conversion efficiency of up to 4.38% under simulated standard AM1.5 solar illumination.

High mobility organic thin film transistor and efficient photovoltaic devices using versatile donor-acceptor polymer semiconductor by molecular design

In this work, we report a novel donor-acceptor based solution processable low band gap polymer semiconductor, PDPP-TNT, synthesized via Suzuki coupling using condensed diketopyrrolopyrrole (DPP) as an acceptor moiety with a fused naphthalene donor building block in the polymer backbone. This polymer exhibits p-channel charge transport characteristics when used as the active semiconductor in organic thin-film transistor (OTFT) devices. The hole mobilities of 0.65 cm2 V-1 s-1 and 0.98 cm2 V -1 s-1 are achieved respectively in bottom gate and dual gate OTFT devices with on/off ratios in the range of 105 to 10 7. Additionally, due to its appropriate HOMO (5.29 eV) energy level and optimum optical band gap (1.50 eV), PDPP-TNT is a promising candidate for organic photovoltaic (OPV) applications. When this polymer semiconductor is used as a donor and PC71BM as an acceptor in OPV devices, high power conversion efficiencies (PCE) of 4.7% are obtained. Such high mobility values in OTFTs and high PCE in OPV make PDPP-TNT a very promising polymer semiconductor for a wide range of applications in organic electronics.

Engineering thin film semiconductor gas sensors to increase sensitivity and decrease operation temperature

Thin film nanostructured gas sensors typically operate at temperatures above 400°C, but lower temperature operation is highly desirable, especially for remote area field sensing as this reduces significantly power consumption. We have investigated a range of sensor materials based on both pure and doped tungsten oxide (mainly focusing on Fe-doping), deposited using both thermal evaporation and electron-beam evaporation, and using a variety of post-deposition annealing. The films show excellent sensitivity at operating temperatures as low as 150°C for detection of NO2. There is a definite relationship between the sensitivity and the crystallinity and nanostructure obtained through the deposition and heat treatment processes, as well as variations in the conductivity caused both by doping and heat treatmetn. The ultimate goal of this work is to control the sensing properties, including selectivity to specific gases through the engineering of the electronic properties and the nanostructure of the films.

Automated power semiconductor switching performance feature extraction from experimental double-pulse waveform data

Double-pulse tests are commonly used as a method for assessing the switching performance of power semiconductor switches in a clamped inductive switching application. Data generated from these tests are typically in the form of sampled waveform data captured using an oscilloscope. In cases where it is of interest to explore a multi-dimensional parameter space and corresponding result space it is necessary to reduce the data into key performance metrics via feature extraction. This paper presents techniques for the extraction of switching performance metrics from sampled double-pulse waveform data. The reported techniques are applied to experimental data from characterisation of a cascode gate drive circuit applied to power MOSFETs.

Jet and flash imprint defectivity - Assessment and reduction for semiconductor applications

Defectivity has been historically identified as a leading technical roadblock to the implementation of nanoimprint lithography for semiconductor high volume manufacturing. The lack of confidence in nanoimprint's ability to meet defect requirements originates in part from the industry's past experiences with 1 × lithography and the shortage in enduser generated defect data. SEMATECH has therefore initiated a defect assessment aimed at addressing these concerns. The goal is to determine whether nanoimprint, specifically Jet and Flash Imprint Lithography from Molecular Imprints, is capable of meeting semiconductor industry defect requirements. At this time, several cycles of learning have been completed in SEMATECH's defect assessment, with promising results. J-FIL process random defectivity of < 0.1 def/cm2 has been demonstrated using a 120nm half-pitch template, providing proof of concept that a low defect nanoimprint process is possible. Template defectivity has also improved significantly as shown by a pre-production grade template at 80nm pitch. Cycles of learning continue on feature sizes down to 22nm. © 2011 SPIE.

A new multilevel converter configuration for high power and high quality applications

The Queensland University of Technology (QUT) allows the presentation of theses for the Degree of Doctor of Philosophy in the format of published or submitted papers, where such papers have been published, accepted or submitted during the period of candidature. This thesis is composed of ten published /submitted papers and book chapters of which nine have been published and one is under review. This project is financially supported by an Australian Research Council (ARC) Discovery Grant with the aim of investigating multilevel topologies for high quality and high power applications, with specific emphasis on renewable energy systems. The rapid evolution of renewable energy within the last several years has resulted in the design of efficient power converters suitable for medium and high-power applications such as wind turbine and photovoltaic (PV) systems. Today, the industrial trend is moving away from heavy and bulky passive components to power converter systems that use more and more semiconductor elements controlled by powerful processor systems. However, it is hard to connect the traditional converters to the high and medium voltage grids, as a single power switch cannot stand at high voltage. For these reasons, a new family of multilevel inverters has appeared as a solution for working with higher voltage levels. Besides this important feature, multilevel converters have the capability to generate stepped waveforms. Consequently, in comparison with conventional two-level inverters, they present lower switching losses, lower voltage stress across loads, lower electromagnetic interference (EMI) and higher quality output waveforms. These properties enable the connection of renewable energy sources directly to the grid without using expensive, bulky, heavy line transformers. Additionally, they minimize the size of the passive filter and increase the durability of electrical devices. However, multilevel converters have only been utilised in very particular applications, mainly due to the structural limitations, high cost and complexity of the multilevel converter system and control. New developments in the fields of power semiconductor switches and processors will favor the multilevel converters for many other fields of application. The main application for the multilevel converter presented in this work is the front-end power converter in renewable energy systems. Diode-clamped and cascade converters are the most common type of multilevel converters widely used in different renewable energy system applications. However, some drawbacks – such as capacitor voltage imbalance, number of components, and complexity of the control system – still exist, and these are investigated in the framework of this thesis. Various simulations using software simulation tools are undertaken and are used to study different cases. The feasibility of the developments is underlined with a series of experimental results. This thesis is divided into two main sections. The first section focuses on solving the capacitor voltage imbalance for a wide range of applications, and on decreasing the complexity of the control strategy on the inverter side. The idea of using sharing switches at the output structure of the DC-DC front-end converters is proposed to balance the series DC link capacitors. A new family of multioutput DC-DC converters is proposed for renewable energy systems connected to the DC link voltage of diode-clamped converters. The main objective of this type of converter is the sharing of the total output voltage into several series voltage levels using sharing switches. This solves the problems associated with capacitor voltage imbalance in diode-clamped multilevel converters. These converters adjust the variable and unregulated DC voltage generated by renewable energy systems (such as PV) to the desirable series multiple voltage levels at the inverter DC side. A multi-output boost (MOB) converter, with one inductor and series output voltage, is presented. This converter is suitable for renewable energy systems based on diode-clamped converters because it boosts the low output voltage and provides the series capacitor at the output side. A simple control strategy using cross voltage control with internal current loop is presented to obtain the desired voltage levels at the output voltage. The proposed topology and control strategy are validated by simulation and hardware results. Using the idea of voltage sharing switches, the circuit structure of different topologies of multi-output DC-DC converters – or multi-output voltage sharing (MOVS) converters – have been proposed. In order to verify the feasibility of this topology and its application, steady state and dynamic analyses have been carried out. Simulation and experiments using the proposed control strategy have verified the mathematical analysis. The second part of this thesis addresses the second problem of multilevel converters: the need to improve their quality with minimum cost and complexity. This is related to utilising asymmetrical multilevel topologies instead of conventional multilevel converters; this can increase the quality of output waveforms with a minimum number of components. It also allows for a reduction in the cost and complexity of systems while maintaining the same output quality, or for an increase in the quality while maintaining the same cost and complexity. Therefore, the asymmetrical configuration for two common types of multilevel converters – diode-clamped and cascade converters – is investigated. Also, as well as addressing the maximisation of the output voltage resolution, some technical issues – such as adjacent switching vectors – should be taken into account in asymmetrical multilevel configurations to keep the total harmonic distortion (THD) and switching losses to a minimum. Thus, the asymmetrical diode-clamped converter is proposed. An appropriate asymmetrical DC link arrangement is presented for four-level diode-clamped converters by keeping adjacent switching vectors. In this way, five-level inverter performance is achieved for the same level of complexity of the four-level inverter. Dealing with the capacitor voltage imbalance problem in asymmetrical diodeclamped converters has inspired the proposal for two different DC-DC topologies with a suitable control strategy. A Triple-Output Boost (TOB) converter and a Boost 3-Output Voltage Sharing (Boost-3OVS) converter connected to the four-level diode-clamped converter are proposed to arrange the proposed asymmetrical DC link for the high modulation indices and unity power factor. Cascade converters have shown their abilities and strengths in medium and high power applications. Using asymmetrical H-bridge inverters, more voltage levels can be generated in output voltage with the same number of components as the symmetrical converters. The concept of cascading multilevel H-bridge cells is used to propose a fifteen-level cascade inverter using a four-level H-bridge symmetrical diode-clamped converter, cascaded with classical two-level Hbridge inverters. A DC voltage ratio of cells is presented to obtain maximum voltage levels on output voltage, with adjacent switching vectors between all possible voltage levels; this can minimize the switching losses. This structure can save five isolated DC sources and twelve switches in comparison to conventional cascade converters with series two-level H bridge inverters. To increase the quality in presented hybrid topology with minimum number of components, a new cascade inverter is verified by cascading an asymmetrical four-level H-bridge diode-clamped inverter. An inverter with nineteen-level performance was achieved. This synthesizes more voltage levels with lower voltage and current THD, rather than using a symmetrical diode-clamped inverter with the same configuration and equivalent number of power components. Two different predictive current control methods for the switching states selection are proposed to minimise either losses or THD of voltage in hybrid converters. High voltage spikes at switching time in experimental results and investigation of a diode-clamped inverter structure raised another problem associated with high-level high voltage multilevel converters. Power switching components with fast switching, combined with hard switched-converters, produce high di/dt during turn off time. Thus, stray inductance of interconnections becomes an important issue and raises overvoltage and EMI issues correlated to the number of components. Planar busbar is a good candidate to reduce interconnection inductance in high power inverters compared with cables. The effect of different transient current loops on busbar physical structure of the high-voltage highlevel diode-clamped converters is highlighted. Design considerations of proper planar busbar are also presented to optimise the overall design of diode-clamped converters.

A modified quality control method for manufacturing process in mask industry

Masks are widely used in different industries, for example, traditional metal industry, hospitals or semiconductor industry. Quality is a critical issue in mask industry as it is related to public health and safety. Traditional quality practices for manufacturing process have some limitations in implementing them in mask industries. This paper aims to investigate the suitability of Six Sigma quality control method for the manufacturing process in the mask industry to provide high quality products, enhancing the process capacity, reducing the defects and the returned goods arising in a selected mask manufacturing company. This paper suggests that modifications necessary in Six Sigma method for effective implementation in mask industry.

Carbon nanotube synthesis from germanium nanoparticles on patterned substrates

Controlled synthesis of carbon nanotubes (CNTs) is highly desirable for nanoelectronic applications. To date, metallic catalyst particles have been deemed unavoidable for the nucleation and growth of any kind of CNTs. Ordered arrays of nanotubes have been obtained by controlled deposition of the metallic catalyst particles. However, the presence of metal species mixed with the CNTs represents a shortcoming for most electronic applications, as metal particles are incompatible with silicon semiconductor technology. In the present paper we report on a metal-catalyst-free synthesis of CNTs, obtained through Ge nanoparticles on a Si(001) surface patterned by nanoindentation. By using acetylene as the carbon feed gas in a low-pressure Chemical Vapor Deposition (CVD) system, multi-walled carbon nanotubes (MWNT) have been observed to arise from the smallest Ge islands. The CNTs and the Ge three-dimensional structures have been analysed by SEM, EDX and AFM in order to assess their elemental features and properties. EDX and SEM results allow confirmation of the absence of any metallic contamination on the surface, indicating that the origin of the CNT growth is due to the Ge nanocrystals.