Dynamic optimization of migration topology in internet-based distributed genetic algorithms

Distributed Genetic Algorithms (DGAs) designed for the Internet have to take its high communication cost into consideration. For island model GAs, the migration topology has a major impact on DGA performance. This paper describes and evaluates an adaptive migration topology optimizer that keeps the communication load low while maintaining high solution quality. Experiments on benchmark problems show that the optimized topology outperforms static or random topologies of the same degree of connectivity. The applicability of the method on real-world problems is demonstrated on a hard optimization problem in VLSI design.

Quantitative assessment of fault tolerant precision timing for electricity substations

Advanced substation applications, such as synchrophasors and IEC 61850-9-2 sampled value process buses, depend upon highly accurate synchronizing signals for correct operation. The IEEE 1588 Precision Timing Protocol (PTP) is the recommended means of providing precise timing for future substations. This paper presents a quantitative assessment of PTP reliability using Fault Tree Analysis. Two network topologies are proposed that use grandmaster clocks with dual network connections and take advantage of the Best Master Clock Algorithm (BMCA) from IEEE 1588. The cross-connected grandmaster topology doubles reliability, and the addition of a shared third grandmaster gives a nine-fold improvement over duplicated grandmasters. The performance of BMCA mediated handover of the grandmaster role during contingencies in the timing system was evaluated experimentally. The 1 µs performance requirement of sampled values and synchrophasors are met, even during network or GPS antenna outages. Slave clocks are shown to synchronize to the backup grandmaster in response to degraded performance or loss of the main grandmaster. Slave disturbances are less than 350 ns provided the grandmaster reference clocks are not offset from one another. A clear understanding of PTP reliability and the factors that affect availability will encourage the adoption of PTP for substation time synchronization.

Evaluation of Attacks and Countermeasures in Large Scale Networks

Computer worms represent a serious threat for modern communication infrastructures. These epidemics can cause great damage such as financial losses or interruption of critical services which support lives of citizens. These worms can spread with a speed which prevents instant human intervention. Therefore automatic detection and mitigation techniques need to be developed. However, if these techniques are not designed and intensively tested in realistic environments, they may cause even more harm as they heavily interfere with high volume communication flows. We present a simulation model which allows studies of worm spread and counter measures in large scale multi-AS topologies with millions of IP addresses.

Hyperprocess

Video presented as part of ACIS 2009 conference in Melbourne Australia. Movie showing the execution of a small prototype Hypbolic projection of a process model. Useful for the traversal of large process models, as the entire hierarchy can be visualised as a whole, maintaining a sense of context while moving through such complex topologies. Related ACIS Conference paper is at: http://eprints.qut.edu.au/29296/

Cascaded DC-DC converter connection of photovoltaic modules

New residential scale photovoltaic (PV) arrays are commonly connected to the grid by a single dc-ac inverter connected to a series string of pv panels, or many small dc-ac inverters which connect one or two panels directly to the ac grid. This paper proposes an alternative topology of nonisolated per-panel dc-dc converters connected in series to create a high voltage string connected to a simplified dc-ac inverter. This offers the advantages of a "converter-per-panel" approach without the cost or efficiency penalties of individual dc-ac grid connected inverters. Buck, boost, buck-boost, and Cu´k converters are considered as possible dc-dc converters that can be cascaded. Matlab simulations are used to compare the efficiency of each topology as well as evaluating the benefits of increasing cost and complexity. The buck and then boost converters are shown to be the most efficient topologies for a given cost, with the buck best suited for long strings and the boost for short strings. While flexible in voltage ranges, buck-boost, and Cu´k converters are always at an efficiency or alternatively cost disadvantage.

High frequency high power converters for industrial applications

The main contribution of this project was to investigate power electronics technology in designing and developing high frequency high power converters for industrial applications. Therefore, the research was conducted at two levels; first at system level which mainly encapsulated the circuit topology and control scheme and second at application level which involves with real-world applications. Pursuing these objectives, varied topologies have been developed and proposed within this research. The main aim was to resolving solid-state switches limited power rating and operating speed while increasing the system flexibility considering the application characteristics. The developed new power converter configurations were applied to pulsed power and high power ultrasound applications for experimental validation.

Diode-clamped three-level inverter-based battery/supercapacitor direct integration scheme for renewable energy systems

This paper describes a diode-clamped three-level inverter-based battery/supercapacitor direct integration scheme for renewable energy systems. The study is carried out for three different cases. In the first case, one of the two dc-link capacitors of the inverter is replaced by a battery bank and the other by a supercapacitor bank. In the second case, dc-link capacitors are replaced by two battery banks. In the third case, ordinary dc-link capacitors are replaced by two supercapacitor banks. The first system is supposed to mitigate both long-term and short-term power fluctuations while the last two systems are intended for smoothening long-term and short-term power fluctuations, respectively. These topologies eliminate the need for interfacing dc-dc converters and thus considerably improve the overall system efficiency. The major issue in aforementioned systems is the unavoidable imbalance in dc-link voltages. An analysis on the effects of unbalance and a space vector modulation method, which can produce undistorted current even in the presence of such unbalances, are presented in this paper. Furthermore, small vector selection-based power sharing and state of charge balancing techniques are proposed. Experimental results, obtained from a laboratory prototype, are presented to verify the efficacy of the proposed modulation and control techniques.

Topological design and modulation strategy for buck-boost three-level inverters

To date, designed topologies for DC-AC inversion with both voltage-buck and boost capabilities are mainly focused on two-level circuitries with extensions to three-level possibilities left nearly unexplored. Contributing to this area of research, this paper presents the design of a number of viable buck-boost three-level inverters that can also support bidirectional power conversion. The proposed front-end circuitry is developed from the Cuk-derived buck-boost two-level inverter, and by using the "alternative phase opposition disposition" (APOD) modulation scheme, the buck-boost three-level inverters can perform distinct five-level line voltage and three-level phase voltage switching by simply controlling the active switches located in the designed voltage boost section of the circuits. As a cost saving option, one active switch can further be removed from the voltage-boost section of the circuits by simply re-routing the gating commands of the remaining switches without influencing the ac output voltage amplitude. To verify the validity of the proposed inverters, Matlab/PLECS simulations were performed before a laboratory prototype was implemented for experimental testing.

Topological design and modulation strategy for buck-boost three-level inverters

To date, designed topologies for DC-AC inversion with both voltage buck and boost capabilities are mainly focused on two-level circuitries with extensions to three-level possibilities left nearly unexplored. Contributing to this area of research, this paper presents the design of a number of viable buck-boost three-level inverters that can also support bidirectional power conversion. The proposed front-end circuitry is developed from the Cuk-derived buck-boost two-level inverter, and by using the ldquoalternative phase opposition dispositionrdquo modulation scheme, the buck-boost three-level inverters can perform distinct five-level line voltage and three-level phase voltage switching by simply controlling the active switches located in the designed voltage boost section of the circuits. As a cost saving option, one active switch can further be removed from the voltage boost section of the circuits by simply rerouting the gating commands of the remaining switches without influencing the AC output voltage amplitude. To verify the validity of the proposed inverters, MATLAB/PLECS simulations were performed before a laboratory prototype was implemented for experimental testing.

An improved gate driver for power MOSFETs using a cascode configuration

To overcome the limitations of existing gate drive topologies an improved gate drive concept is proposed to provide fast, controlled switching of power MOSFETs. The proposed topology exploits the cascode configuration with the inclusion of an active gate clamp to ensure that the driven MOSFET may be turned off under all load conditions. Key operating principles and advantages of the proposed gate drive topology are discussed. Characteristic waveforms are investigated via simulation and experimentation for the cascode driver in an inductive switching application at 375V and 10A. Experimental waveforms compared well with simulations with long gate charging delays (including the Miller plateau) being eliminated from the gate voltage waveform.

Rectifier systems for variable speed wind generation : a review

The drive towards high efficiency wind energy conversion systems has resulted in almost all the modern wind turbines to operate in the variable speed mode which inevitably requires back-to-back power electronic converters to decouple generator dynamics from the grid. The aim of this paper is to present an analysis on suitable topologies for the generator-side converter (rectifier) of the back-to-back converter arrangement. Performance of the two most popular rectifier systems, namely, the passive diode bridge rectifier and the active six-switch two-level rectifier are taken as two extremes to evaluate other topologies presented in this paper. The other rectifier systems considered in this study include combinations of a diode bridge rectifier and electronic reactance(s), a combination of a rectifier and a dc-dc converter and a half controlled rectifier. Diode-clamped and capacitor-clamped three-level active rectifier topologies and their possible switch reductions are also discussed in relation to the requirements of modern high power wind energy conversion systems (WECSs). Simulation results are presented to support conclusion derived from this analysis.

A modular matrix converter for transformer-less PMSG wind generation systems

An offshore wind turbine usually has the grid step-up transformer integrated in the nacelle. This increases mechanical loading of the tower. In that context, a transformer-less, high voltage, highly-reliable and compact converter system for nacelle installation would be an attractive solution for large offshore wind turbines. This paper, therefore, presents a transformer-less grid integration topology for PMSG based large wind turbine generator systems using modular matrix converters. Each matrix converter module is fed from three generator coils of the PMSG which are phase shifted by 120°. Outputs of matrix converter modules are connected in series to increase the output voltage and thus eliminate the need of a coupling step-up transformer. Moreover, dc-link capacitors found in conventional back-to-back converter topologies are eliminated in the proposed system. Proper multilevel output voltage generation and power sharing between converter modules are achieved through an advanced switching strategy. Simulation results are presented to validate the proposed modular matrix converter system, modulation method and control techniques.

Synthesis of orchestrators from service choreographies

Interaction topologies in service-oriented systems are usually classified into two styles: choreographies and orchestrations. In a choreography, services interact in a peer-to-peer manner and no service plays a privileged role. In contrast, interactions in an orchestration occur between one particular service, the orchestrator, and a number of subordinated services. Each of these topologies has its trade-offs. This paper considers the problem of migrating a service-oriented system from a choreography style to an orchestration style. Specifically, the paper presents a tool chain for synthesising orchestrators from choreographies. Choreographies are initially represented as communicating state machines. Based on this representation, an algorithm is presented that synthesises the behaviour of an orchestrator, which is also represented as a state machine. Concurrent regions are then identified in the synthesised state machine to obtain a more compact representation in the form of a Petri net. Finally, it is shown how the resulting Petri nets can be transformed into notations supported by commercial tools, such as the Business Process Modelling Notation (BPMN).

The dynamics of cellular automata on 2-manifolds is affected by topology

In this paper, we demonstrate that the distribution of Wolfram classes within a cellular automata rule space in the triangular tessellation is not consistent across different topological general. Using a statistical mechanics approach, cellular automata dynamical classes were approximated for cellular automata defined on genus-0, genus-1 and genus-2 2-manifolds. A distribution-free equality test for empirical distributions was applied to identify cases in which Wolfram classes were distributed differently across topologies. This result implies that global structure and local dynamics contribute to the long term evolution of cellular automata.

On the effect of topology on cellular automata rule spaces

This thesis presents an empirical study of the effects of topology on cellular automata rule spaces. The classical definition of a cellular automaton is restricted to that of a regular lattice, often with periodic boundary conditions. This definition is extended to allow for arbitrary topologies. The dynamics of cellular automata within the triangular tessellation were analysed when transformed to 2-manifolds of topological genus 0, genus 1 and genus 2. Cellular automata dynamics were analysed from a statistical mechanics perspective. The sample sizes required to obtain accurate entropy calculations were determined by an entropy error analysis which observed the error in the computed entropy against increasing sample sizes. Each cellular automata rule space was sampled repeatedly and the selected cellular automata were simulated over many thousands of trials for each topology. This resulted in an entropy distribution for each rule space. The computed entropy distributions are indicative of the cellular automata dynamical class distribution. Through the comparison of these dynamical class distributions using the E-statistic, it was identified that such topological changes cause these distributions to alter. This is a significant result which implies that both global structure and local dynamics play a important role in defining long term behaviour of cellular automata.