Effects of switching time on output voltages of a multilevel inverter used in high frequency applications

Employing multilevel inverters is a proper solution to reduce harmonic content of output voltage and electromagnetic interference in high power electronic applications. In this paper, a new pulse width modulation method for multilevel inverters is proposed in which power devices’ on-off switching times have been considered. This method can be surveyed in order to analyse the effect of switching time on harmonic contents of output voltage in high frequency applications when a switching time is not negligible compared to a switching cycle. Fast Fourier transform calculation and analysis of output voltage waveforms and harmonic contents with regard to switching time variation are presented in this paper for a single phase (3, 5)-level inverters used in high voltage and high frequency converters. Mathematical analysis and MATLAB simulation results have been carried out to validate the proposed method.

A restrike waveform predictive model for shunt capacitor bank switching with point-on-wave recommendation

Circuit-breakers (CBs) are subject to electrical stresses with restrikes during capacitor bank operation. Stresses are caused by the overvoltages across CBs, the interrupting currents and the rate of rise of recovery voltage (RRRV). Such electrical stresses also depend on the types of system grounding and the types of dielectric strength curves. The aim of this study is to demonstrate a restrike waveform predictive model for a SF6 CB that considered the types of system grounding: grounded and non-grounded and the computation accuracy comparison on the application of the cold withstand dielectric strength and the hot recovery dielectric strength curve including the POW (point-on-wave) recommendations to make an assessment of increasing the CB remaining life. The simulation of SF6 CB stresses in a typical 400 kV system was undertaken and the results in the applications are presented. The simulated restrike waveforms produced with the identified features using wavelet transform can be used for restrike diagnostic algorithm development with wavelet transform to locate a substation with breaker restrikes. This study found that the hot withstand dielectric strength curve has less magnitude than the cold withstand dielectric strength curve for restrike simulation results. Computation accuracy improved with the hot withstand dielectric strength and POW controlled switching can increase the life for a SF6 CB.

A method of extracting switching loss from a high efficiency MOSFET based half bridge converter

The measurement of losses in high efficiency / high power converters is difficult. Measuring the losses directly from the difference between the input and output power results in large errors. Calorimetric methods are usually used to bypass this issue but introduce different problems, such as, long measurement times, limited power loss measurement range and/or large set up cost. In this paper the total losses of a converter are measured directly and switching losses are exacted. The measurements can be taken with only three multimeters and a current probe and a standard bench power supply. After acquiring two or three power loss versus output current sweeps, a series of curve fitting processes are applied and the switching losses extracted.

Voltage unbalance reduction in low voltage feeders by dynamic switching of residential customers among three phases

Low voltage distribution feeders with large numbers of single phase residential loads experience severe current unbalance that often causes voltage unbalance problems. The addition of intermittent generation and new loads in the form of roof top photovoltaic generation and electric vehicles makes these problems even more acute. In this paper, an intelligent dynamic residential load transfer scheme is proposed. Residential loads can be transferred from one phase to another phase to minimize the voltage unbalance along the feeder. Each house is supplied through a static transfer switch with three-phase input and single-phase output connection. The main controller, installed at the transformer will observe the power consumption in each load and determine which house(s) should be transferred from one phase to another in order to keep the voltage unbalance in the feeder at a minimum. The efficacy of the proposed load transfer scheme is verified through MATLAB and PSCAD/EMTDC simulations.

Smart Inter-Phase Switching of Residential Loads in Low Voltage Distribution Feeders

In order to dynamically reduce voltage unbalance along a low voltage distribution feeder, a smart residential load transfer system is discussed. In this scheme, residential loads can be transferred from one phase to another to minimize the voltage unbalance along the feeder. Each house is supplied through a static transfer switch and a controller. The master controller, installed at the transformer, observes the power consumption in each house and will determine which house(s) should be transferred from an initially connected phase to another in order to keep the voltage unbalance minimum. The performance of the smart load transfer scheme is demonstrated by simulations.

Universal codes from switching strategies

We discuss algorithms for combining sequential prediction strategies, a task which can be viewed as a natural generalisation of the concept of universal coding. We describe a graphical language based on Hidden Markov Models for defining prediction strategies, and we provide both existing and new models as examples. The models include efficient, parameterless models for switching between the input strategies over time, including a model for the case where switches tend to occur in clusters, and finally a new model for the scenario where the prediction strategies have a known relationship, and where jumps are typically between strongly related ones. This last model is relevant for coding time series data where parameter drift is expected. As theoretical contributions we introduce an interpolation construction that is useful in the development and analysis of new algorithms, and we establish a new sophisticated lemma for analysing the individual sequence regret of parameterised models.

Dual Z-source inverter with three-level reduced common mode switching

This paper presents the design of a dual Z-source inverter that can be used with either a single dc source or two isolated dc sources. Unlike traditional inverters, the integration of a properly designed Z-source network and semiconductor switches to the proposed dual inverter allows buck-boost power conversion to be performed over a wide modulation range with three-level output waveforms generated. The connection of an additional transformer to the inverter ac output also allows all generic wye- or delta-connected loads with three-wire or four-wire configuration to be supplied by the inverter. Modulation-wise, the dual inverter can be controlled using a carefully designed carrier-based pulse-width modulation (PWM) scheme that always will ensure balanced voltage boosting of the Z-source network, while simultaneously achieving reduced common-mode switching. Because of the omission of dead-time delays in the dual inverter PWM scheme, its switched common-mode voltage can be completely eliminated, unlike in traditional inverters where narrow common-mode spikes are still generated. Under semiconductor failure conditions, the presented PWM schemes can easily be modified to allow the inverter to operate without interruption and for cases where two isolated sources are used, zero common-mode voltage can still be ensured. These theoretical findings together with the inverter practicality have been confirmed both in simulations using PSIM with Matlab/Simulink coupler and experimentally using a laboratory implemented inverter prototype.

Dual Z-source inverter with three-level reduced common-mode switching

This paper presents the design of a dual Z-source inverter that can be used with either a single dc source or two isolated dc sources. Unlike traditional inverters, the integration of a properly designed Z-source network and semiconductor switches to the proposed dual inverter allows buck-boost power conversion to be performed over a wide modulation range, with three-level output waveforms generated. The connection of an additional transformer to the inverter ac output also allows all generic wye-or delta-connected loads with three-wire or four-wire configuration to be supplied by the inverter. Modulationwise, the dual inverter can be controlled using a carefully designed carrier-based pulsewidth-modulation (PWM) scheme that will always ensure balanced voltage boosting of the Z-source network while simultaneously achieving reduced common-mode switching. Because of the omission of dead-time delays in the dual-inverter PWM scheme, its switched common-mode voltage can be completely eliminated, unlike in traditional inverters, where narrow common-mode spikes are still generated. Under semiconductor failure conditions, the presented PWM schemes can easily be modified to allow the inverter to operate without interruption, and for cases where two isolated sources are used, zero common-mode voltage can still be ensured. These theoretical findings, together with the inverter practicality, have been confirmed in simulations both using PSIM with Matlab/Simulink coupler and experimentally using a laboratory-implemented inverter prototype.

Mode switching DFIG for low voltage ride through

With the rapid development of world-wide wind energy generation using doubly fed induction generations (DFIGs), low voltage ride through (LVRT) has become a great concern. This paper focuses on a unique topology of DFIG called IG connection mode to help the DFIG ride through grid faults smoothly. Transient analysis of IG connection mode is carried out to derive the generator currents. With this analysis, the control strategy for IG connection mode DFIG was developed. From the simulation results, it is clearly visible that IG mode could work in both normal and low grid voltage conditions. Simulation results clearly show that the DFIG with the proposed mode switching control could smoothly ride through low voltage grid faults while satisfying grid code requirements.

Optimized switching control strategy for current-fed half-bridge converter

A switching control strategy is proposed for current-fed half-bridge converters. An active switch based voltage doubler circuit at the secondary side of the isolation transformer is used to obtain zero-current-switching at turn-off and zero-voltage-switching at turn-on in the primary side switches of the current-fed half-bridge converter. The operation of the current-fed half-bridge converter with the proposed switching control strategy is explained using the equivalent circuit during each sub-interval of operation. The operation of the current-fed halfbridge converter is simulated using MATLAB/Simpower and PSIM to verify the feasibility of the switching control strategy. Experimental results are provided to validate the converter's operation.

Design of mode switching scheme for low-voltage ride-through of doubly fed induction generators

A mode switching doubly fed induction generator (MSDFIG) scheme is proposed for the purpose of achieving low-voltage ride-through for wind turbines. The MSDFIG operates as a doubly fed induction generator (DFIG) under normal condition but upon the detection of a low-voltage incident, the generator is to smoothly transfer to operate under the induction generator mode through the switching in of a set of stator-side crowbar. The MSDFIG automatically reverts back to the DFIG mode when network voltage recovers. A new strategy on the control of the crowbar resistance is included. Analysis shows that the proposed MSDFIG scheme can ride through the complete low-voltage and voltage recovery stages. Effectiveness of the scheme is demonstrated through simulation and experiment studies.

Automated power semiconductor switching performance feature extraction from experimental double-pulse waveform data

Double-pulse tests are commonly used as a method for assessing the switching performance of power semiconductor switches in a clamped inductive switching application. Data generated from these tests are typically in the form of sampled waveform data captured using an oscilloscope. In cases where it is of interest to explore a multi-dimensional parameter space and corresponding result space it is necessary to reduce the data into key performance metrics via feature extraction. This paper presents techniques for the extraction of switching performance metrics from sampled double-pulse waveform data. The reported techniques are applied to experimental data from characterisation of a cascode gate drive circuit applied to power MOSFETs.