Controlled Growth of ZnO Tetrapods: Influence of Temperature and Temperature Gradient

Though it has been established that ZnO tetrapods can be synthesized by heating Zn in air, it is advantageous to grow tetrapods with legs of different morphologies with different lengths. Here, we report the large scale synthesis of ZnO tetrapods by heating Zn in air ambient. The parameters that control the diameter, length, and morphology of tetrapods are identified. It is shown that the morphology and dimensions of the tetrapods depend not only on the vaporization temperature but also on the temperature gradient of the furnace. The controlled synthesis procedure and the key parameters that influence the morphology are discussed.

Adaptive Keeper Design for Dynamic Logic Circuits Using Rate Sensing Technique

The increasing variability in device leakage has made the design of keepers for wide OR structures a challenging task. The conventional feedback keepers (CONV) can no longer improve the performance of wide dynamic gates for the future technologies. In this paper, we propose an adaptive keeper technique called rate sensing keeper (RSK) that enables faster switching and tracks the variation across different process corners. It can switch upto 1.9x faster (for 20 legs) than CONV and can scale upto 32 legs as against 20 legs for CONV in a 130-nm 1.2-V process. The delay tracking is within 8% across the different process corners. We demonstrate the circuit operation of RSK using a 32 x 8 register file implemented in an industrial 130-nm 1.2-V CMOS process. The performance of individual dynamic logic gates are also evaluated on chip for various keeper techniques. We show that the RSK technique gives superior performance compared to the other alternatives such as Conditional Keeper (CKP) and current mirror-based keeper (LCR).

Multilevel inverters for low-power application

Multilevel inverters are an attractive solution in the medium-voltage and high-power applications. However in the low-power range also it can be a better solution compared to two-level inverters, if MOSFETs are used as devices switching in the order of 100 kHz. The effect of clamping diodes in the diode-clamped multilevel inverters play an important role in determining its efficiency. Power loss introduced by the reverse recovery of MOSFET body diode prohibits the use of MOSFET in hard-switched inverter legs. A technique of avoiding reverse recovery loss of MOSFET body diode in a three-level neutral point clamped inverter is suggested. The use of multilevel inverters topology enables operation at high switching frequency without sacrificing efficiency. High switching frequency of operation reduces the output filter requirement, which in turn helps in reducing the size of the inverter. This study elaborates the trade-off analysis to quantify the suitability of multilevel inverters in the low-power applications. Advantages of using a MOSFET-based three-level diode-clamped inverter for a PM motor drive and UPS systems are discussed.

Proportional resonant controller based circulating power setup for thermal testing of multilevel inverter

A regenerative or circulating-power method is presented in this paper for heat run test on the legs of a three-level neutral point clamped (NPC) inverter. This test ensures that only losses are drawn from the dc supply, while rated power is circulated between the two legs, thus minimising wastage of energy. A proportional-resonant (PR) controller based current control scheme is proposed here for the circulating power test setup in NPC inverter. Simulation and experimental results are presented to validate the controller design at various operating conditions. Results of thermal test on the inverter legs are presented at two different operating conditions.

Design and Development of Thermoelectric Generator

In this paper we discuss the fabrication, working and characteristics of a thermoelectric generator made up of p and n type semiconductor materials. The device consists of Fe0.2Co3.8Sb11.5Te0.5 (zT = 1.04 at 818 K) as the n-type and Zn4Sb3 (zT= 0.8 at 550 K) as the p-type material synthesized by vacuum hot press method. Carbon paste has been used to join the semiconductor legs to metal (Molybdenum) electrodes to reduce the contact resistance. The multi-couple (4 legs) generator results a maximum output power of 1.083 mW at a temperature difference of 240 K between the hot and cold sides. In this investigation, an I-V characteristic, maximum output power of the thermoelectric module is presented. The efficiency of thermoelectric module is obtained as eta= 0.273 %.

Filter Configuration and PWM Method For Single Phase Inverters with Reduced Conducted EMI Noise

Electromagnetic Interference (EMI) noise is one of the major issues during the design of the grid-tied power converters. Presence of high dv/dt in Common Mode (CM) voltage, excites the parasitic capacitances and causes injection of narrow peaky current to ground. This results in high EMI noise level. A topology consisting of a single phase PWM-rectifier with LCL filter, utilising bipolar PWM method is proposed which reduces the EMI noise level by more than 30dB. This filter topology is shown to be insensitive to the switching delays between the legs of the inverter. The proposed topology eliminates high dv/dt from the dc-bus CM voltage by making it sinusoidal. Hence, the high frequency CM current injection to ground is minimized.

Filter Configuration and PWM Method For Single-Phase Inverters With Reduced Conducted EMI Noise

Electromagnetic interference (EMI) noise is one of the major issues during design of grid-tied power converters. A novel LCL filter topology for a single-phase pulsewidth modulation (PWM) rectifier that makes use of bipolar PWM method is proposed for a single-phase to three-phase motor drive power converter. The proposed topology eliminates high dv/dt from the dc-bus common-mode (CM) voltage by making it sinusoidal. Hence, the high-frequency CM current injection to the ground and the motor-side CM current are minimized. The proposed filter configuration makes the system insensitive to circuit non-idealities such as mismatch in inductors values, unequal turn-on and turn-off delays, and dead-time mismatch between the inverter legs. Different variants of the filter topology are compared to establish the effectiveness of the proposed circuit. Experimental results based on the EMI measurement on the grid side and the CM current measurement on the motor side are presented for a 5-kW motor drive. It is shown that the proposed filter topology reduces the EMI noise level by about 35 dB.

Thermal test method for high power three-phase grid-connected inverters

Semiconductor device junction temperatures are maintained within datasheet specified limits to avoid failure in power converters. Burn-in tests are used to ensure this. In inverters, thermal time constants can be large and burn-in tests are required to be performed over long durations of time. At higher power levels, besides increased production cost, the testing requires sources and loads that can handle high power. In this study, a novel method to test a high power three-phase grid-connected inverter is proposed. The method eliminates the need for high power sources and loads. Only energy corresponding to the losses is consumed. The test is done by circulating rated current within the three legs of the inverter. All the phase legs being loaded, the method can be used to test the inverter in both cases of a common or independent cooling arrangement for the inverter phase legs. Further, the method can be used with different inverter configurations - three- or four-wire and for different pulse width modulation (PWM) techniques. The method has been experimentally validated on a 24 kVA inverter for a four-wire configuration that uses sine-triangle PWM and a three-wire configuration that uses conventional space vector PWM.