84 resultados para lab-on-a-chip systems

em Indian Institute of Science - Bangalore - Índia


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Sensitivity analysis is an important aspect to be looked into while designing lab-on-a-chip systems. In this paper we will be showing with appropriate design that the best sensitivity of the fluorescence biosensor is achieved for an optimal width of fluidic gap, corresponding to a particular mode spot size. We will be also showing that the sensitivity of the biosensor is affected by efficiency of light coupling, which is influenced by changes in the width of fluidic gap, refractive index of the fluid and higher order modes.

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In this paper we will be presenting the effect of fluidic gap, the effect of change of refractive index of the fluid contained in the gap, and the effect of higher order modes on the efficiency of light coupling and thus on the on the sensitivity of the sensor.

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In this paper we will be presenting the effect of fluidic gap, the effect of change of refractive index of the fluid contained in the gap, and the effect of higher order modes on the efficiency of light coupling and thus on the on the sensitivity of the sensor.

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The analysis of a fully integrated optofluidic lab-on-a-chip sensor is presented in this paper. This device is comprised of collinear input and output waveguides that are separated by a microfluidic channel. When light is passed through the analyte contained in the fluidic gap, optical power loss occurs owing to absorption of light. Apart from absorption, a mode-mismatch between the input and output waveguides occurs when the light propagates through the fluidic gap. The degree of mode-mismatch and quantum of optical power loss due to absorption of light by the fluid form the basis of our analysis. This sensor can detect changes in refractive index and changes in concentration of species contained in the analyte. The sensitivity to detect minute changes depends on many parameters. The parameters that influence the sensitivity of the sensor are mode spot size, refractive index of the fluid, molar concentration of the species contained in the analyte, width of the fluidic gap, and waveguide geometry. By correlating various parameters, an optimal fluidic gap distance corresponding to a particular mode spot size that achieves the best sensitivity is determined both for refractive index and absorbance-based sensing.

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DNA amplification using Polymerase Chain Reaction (PCR) in a small volume is used in Lab-on-a-chip systems involving DNA manipulation. For few microliters of volume of liquid, it becomes difficult to measure and monitor the thermal profile accurately and reproducibly, which is an essential requirement for successful amplification. Conventional temperature sensors are either not biocompatible or too large and hence positioned away from the liquid leading to calibration errors. In this work we present a fluorescence based detection technique that is completely biocompatible and measures directly the liquid temperature. PCR is demonstrated in a 3 ILL silicon-glass microfabricated device using non-contact induction heating whose temperature is controlled using fluorescence feedback from SYBR green I dye molecules intercalated within sensor DNA. The performance is compared with temperature feedback using a thermocouple sensor. Melting curve followed by gel electrophoresis is used to confirm product specificity after the PCR cycles. (c) 2007 Elsevier B.V. All rights reserved.

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Exascale systems of the future are predicted to have mean time between failures (MTBF) of less than one hour. Malleable applications, where the number of processors on which the applications execute can be changed during executions, can make use of their malleability to better tolerate high failure rates. We present AdFT, an adaptive fault tolerance framework for long running malleable applications to maximize application performance in the presence of failures. AdFT framework includes cost models for evaluating the benefits of various fault tolerance actions including checkpointing, live-migration and rescheduling, and runtime decisions for dynamically selecting the fault tolerance actions at different points of application execution to maximize performance. Simulations with real and synthetic failure traces show that our approach outperforms existing fault tolerance mechanisms for malleable applications yielding up to 23% improvement in application performance, and is effective even for petascale systems and beyond.

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Advances in technology have increased the number of cores and size of caches present on chip multicore platforms(CMPs). As a result, leakage power consumption of on-chip caches has already become a major power consuming component of the memory subsystem. We propose to reduce leakage power consumption in static nonuniform cache architecture(SNUCA) on a tiled CMP by dynamically varying the number of cache slices used and switching off unused cache slices. A cache slice in a tile includes all cache banks present in that tile. Switched-off cache slices are remapped considering the communication costs to reduce cache usage with minimal impact on execution time. This saves leakage power consumption in switched-off L2 cache slices. On an average, there map policy achieves 41% and 49% higher EDP savings compared to static and dynamic NUCA (DNUCA) cache policies on a scalable tiled CMP, respectively.

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This report summarizes the presentations and discussions conducted during the symposium, which was held under the aegis of the International Union of Theoretical and Applied Mechanics during 23-27 January 2012 in Bangalore, India. (C) 2013 AIP Publishing LLC.

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Prediction of queue waiting times of jobs submitted to production parallel batch systems is important to provide overall estimates to users and can also help meta-schedulers make scheduling decisions. In this work, we have developed a framework for predicting ranges of queue waiting times for jobs by employing multi-class classification of similar jobs in history. Our hierarchical prediction strategy first predicts the point wait time of a job using dynamic k-Nearest Neighbor (kNN) method. It then performs a multi-class classification using Support Vector Machines (SVMs) among all the classes of the jobs. The probabilities given by the SVM for the class predicted using k-NN and its neighboring classes are used to provide a set of ranges of predicted wait times with probabilities. We have used these predictions and probabilities in a meta-scheduling strategy that distributes jobs to different queues/sites in a multi-queue/grid environment for minimizing wait times of the jobs. Experiments with different production supercomputer job traces show that our prediction strategies can give correct predictions for about 77-87% of the jobs, and also result in about 12% improved accuracy when compared to the next best existing method. Experiments with our meta-scheduling strategy using different production and synthetic job traces for various system sizes, partitioning schemes and different workloads, show that the meta-scheduling strategy gives much improved performance when compared to existing scheduling policies by reducing the overall average queue waiting times of the jobs by about 47%.

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Exascale systems of the future are predicted to have mean time between failures (MTBF) of less than one hour. At such low MTBFs, employing periodic checkpointing alone will result in low efficiency because of the high number of application failures resulting in large amount of lost work due to rollbacks. In such scenarios, it is highly necessary to have proactive fault tolerance mechanisms that can help avoid significant number of failures. In this work, we have developed a mechanism for proactive fault tolerance using partial replication of a set of application processes. Our fault tolerance framework adaptively changes the set of replicated processes periodically based on failure predictions to avoid failures. We have developed an MPI prototype implementation, PAREP-MPI that allows changing the replica set. We have shown that our strategy involving adaptive process replication significantly outperforms existing mechanisms providing up to 20 percent improvement in application efficiency even for exascale systems.

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In this work, we have demonstrated three unique regimes in the evaporation lifecycle of a pair of sessile droplets placed in variable proximity on a hydrophobic substrate. For small separation distance, the droplets undergo asymmetric spatiotemporal,evaporation leading to contact angle hysteresis and suppressed vaporization. The reduced evaporation has been attributed quantitatively to the existence of a constrained vapor-rich dome between the two droplets. However, a dynamic decrease in the droplet radius due to solvent removal marks a return to symmetry in terms of evaporation and contact angle. We have described the variation in evaporation flux using a universal correction factor. We have also demonstrated the existence of a critical separation distance beyond which the droplets in the, droplet pair do not affect each other. The results are crucial to a plethora of applications ranging from surface patterning to lab-on-a-chip devices.

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In this work, we have demonstrated three unique regimes in the evaporation lifecycle of a pair of sessile droplets placed in variable proximity on a hydrophobic substrate. For small separation distance, the droplets undergo asymmetric spatiotemporal,evaporation leading to contact angle hysteresis and suppressed vaporization. The reduced evaporation has been attributed quantitatively to the existence of a constrained vapor-rich dome between the two droplets. However, a dynamic decrease in the droplet radius due to solvent removal marks a return to symmetry in terms of evaporation and contact angle. We have described the variation in evaporation flux using a universal correction factor. We have also demonstrated the existence of a critical separation distance beyond which the droplets in the, droplet pair do not affect each other. The results are crucial to a plethora of applications ranging from surface patterning to lab-on-a-chip devices.

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Today's SoCs are complex designs with multiple embedded processors, memory subsystems, and application specific peripherals. The memory architecture of embedded SoCs strongly influences the power and performance of the entire system. Further, the memory subsystem constitutes a major part (typically up to 70%) of the silicon area for the current day SoC. In this article, we address the on-chip memory architecture exploration for DSP processors which are organized as multiple memory banks, where banks can be single/dual ported with non-uniform bank sizes. In this paper we propose two different methods for physical memory architecture exploration and identify the strengths and applicability of these methods in a systematic way. Both methods address the memory architecture exploration for a given target application by considering the application's data access characteristics and generates a set of Pareto-optimal design points that are interesting from a power, performance and VLSI area perspective. To the best of our knowledge, this is the first comprehensive work on memory space exploration at physical memory level that integrates data layout and memory exploration to address the system objectives from both hardware design and application software development perspective. Further we propose an automatic framework that explores the design space identifying 100's of Pareto-optimal design points within a few hours of running on a standard desktop configuration.

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In this paper, we are interested in high spectral efficiency multicode CDMA systems with large number of users employing single/multiple transmit antennas and higher-order modulation. In particular, we consider a local neighborhood search based multiuser detection algorithm which offers very good performance and complexity, suited for systems with large number of users employing M-QAM/M-PSK. We apply the algorithm on the chip matched filter output vector. We demonstrate near-single user (SU) performance of the algorithm in CDMA systems with large number of users using 4-QAM/16-QAM/64-QAM/8-PSK on AWGN, frequency-flat, and frequency-selective fading channels. We further show that the algorithm performs very well in multicode multiple-input multiple-output (MIMO) CDMA systems as well, outperforming other linear detectors and interference cancelers reported in the literature for such systems. The per-symbol complexity of the search algorithm is O(K2n2tn2cM), K: number of users, nt: number of transmit antennas at each user, nc: number of spreading codes multiplexed on each transmit antenna, M: modulation alphabet size, making the algorithm attractive for multiuser detection in large-dimension multicode MIMO-CDMA systems with M-QAM.