Models of reserve manpower

Absenteeism is one of the major problems of Indian industries. It necessitates the employment of more manpower than the jobs require, resulting in the increase of manpower costs, and lowers the efficiency of plant operation through lowered performance and higher rejects. It also causes machine idleness, if extra manpower is not hired, resulting in disrupted work schedules and assignments. Several studies have investigated the causes of absenteeism (Vaid 1967) for example and their remedy and relationship between absenteeism and turnover with a suggested model for diagnosis and treatment (Hawk 1976) However, the production foremen and supervisor will face the operating task of determining how many extra operatives are to be hired in order to stave off the adverse effects of absenteeism on the man-machine system. This paper deals with a class of reserve manpower models based on the reject allowance model familiar in quality control literature. The present study considers, in addition to absenteeism, machine failures and the graded nature of manpower met within production systems and seeks to find optimal reserve manpower through computer simulation.

Compiler Assisted Leakage Energy Optimization for Clustered VLIW Architectures

Miniaturization of devices and the ensuing decrease in the threshold voltage has led to a substantial increase in the leakage component of the total processor energy consumption. Relatively simpler issue logic and the presence of a large number of function units in the VLIW and the clustered VLIW architectures attribute a large fraction of this leakage energy consumption in the functional units. However, functional units are not fully utilized in the VLIW architectures because of the inherent variations in the ILP of the programs. This underutilization is even more pronounced in the context of clustered VLIW architectures because of the contentions for the limited number of slow intercluster communication channels which lead to many short idle cycles.In the past, some architectural schemes have been proposed to obtain leakage energy bene .ts by aggressively exploiting the idleness of functional units. However, presence of many short idle cycles cause frequent transitions from the active mode to the sleep mode and vice-versa and adversely a ffects the energy benefits of a purely hardware based scheme. In this paper, we propose and evaluate a compiler instruction scheduling algorithm that assist such a hardware based scheme in the context of VLIW and clustered VLIW architectures. The proposed scheme exploits the scheduling slacks of instructions to orchestrate the functional unit mapping with the objective of reducing the number of transitions in functional units thereby keeping them off for a longer duration. The proposed compiler-assisted scheme obtains a further 12% reduction of energy consumption of functional units with negligible performance degradation over a hardware-only scheme for a VLIW architecture. The benefits are 15% and 17% in the context of a 2-clustered and a 4-clustered VLIW architecture respectively. Our test bed uses the Trimaran compiler infrastructure.