234 resultados para electronic components

em Indian Institute of Science - Bangalore - Índia


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The temperature variation in the insulation around an electronic component, mounted on a horizontal circuit board is studied numerically. The flow is assumed to be laminar and fully developed. The effect of mixed convection and two different types of insulation are considered. The mass, momentum and energy conservation equations in the fluid and conduction equation in the insulation are solved using the SIMPLER algorithm. Computations are carried out for liquid Freon and water, for different conductivity ratios, and different Rayleigh numbers. It is demonstrated that the temperature variation within the insulation becomes important when the thermal conductivity of the insulation is less than ten times the thermal conductivity of the cooling medium.

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A laboratory model of a thermally driven adsorption refrigeration system with activated carbon as the adsorbent and 1,1,1,2-tetrafluoroethane (HFC 134a) as the refrigerant was developed. The single stage compression system has an ensemble of four adsorbers packed with Maxsorb II specimen of activated carbon that provide a near continuous flow which caters to a cooling load of up to 5W in the 5-18 degrees C region. The objective was to utilise the low grade thermal energy to drive a refrigeration system that can be used to cool some critical electronic components. The laboratory model was tested for it performance at various cooling loads with the heat source temperature from 73 to 93 degrees C. The pressure transients during heating and cooling phases were traced. The cyclic steady state and transient performance data are presented. (C) 2010 Elsevier Ltd. All rights reserved.

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One of the foremost design considerations in microelectronics miniaturization is the use of embedded passives which provide practical solution. In a typical circuit, over 80 percent of the electronic components are passives such as resistors, inductors, and capacitors that could take up to almost 50 percent of the entire printed circuit board area. By integrating passive components within the substrate instead of being on the surface, embedded passives reduce the system real estate, eliminate the need for discrete and assembly, enhance electrical performance and reliability, and potentially reduce the overall cost. Moreover, it is lead free. Even with these advantages, embedded passive technology is at a relatively immature stage and more characterization and optimization are needed for practical applications leading to its commercialization.This paper presents an entire process from design and fabrication to electrical characterization and reliability test of embedded passives on multilayered microvia organic substrate. Two test vehicles focusing on resistors and capacitors have been designed and fabricated. Embedded capacitors in this study are made with polymer/ceramic nanocomposite (BaTiO3) material to take advantage of low processing temperature of polymers and relatively high dielectric constant of ceramics and the values of these capacitors range from 50 pF to 1.5 nF with capacitance per area of approximately 1.5 nF/cm(2). Limited high frequency measurement of these capacitors was performed. Furthermore, reliability assessments of thermal shock and temperature humidity tests based on JEDEC standards were carried out. Resistors used in this work have been of three types: 1) carbon ink based polymer thick film (PTF), 2) resistor foils with known sheet resistivities which are laminated to printed wiring board (PWB) during a sequential build-up (SBU) process and 3) thin-film resistor plating by electroless method. Realization of embedded resistors on conventional board-level high-loss epoxy (similar to 0.015 at 1 GHz) and proposed low-loss BCB dielectric (similar to 0.0008 at > 40 GHz) has been explored in this study. Ni-P and Ni-W-P alloys were plated using conventional electroless plating, and NiCr and NiCrAlSi foils were used for the foil transfer process. For the first time, Benzocyclobutene (BCB) has been proposed as a board level dielectric for advanced System-on-Package (SOP) module primarily due to its attractive low-loss (for RF application) and thin film (for high density wiring) properties.Although embedded passives are more reliable by eliminating solder joint interconnects, they also introduce other concerns such as cracks, delamination and component instability. More layers may be needed to accommodate the embedded passives, and various materials within the substrate may cause significant thermo -mechanical stress due to coefficient of thermal expansion (CTE) mismatch. In this work, numerical models of embedded capacitors have been developed to qualitatively examine the effects of process conditions and electrical performance due to thermo-mechanical deformations.Also, a prototype working product with the board level design including features of embedded resistors and capacitors are underway. Preliminary results of these are presented.

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During experiments carried out to find out a suitable contact metal for electronic components based on high-T(c) superconductor films (Y-Ba-Cu-O), it is observed that there is an asymmetry in the U-I characteristics if the two contacts are made of different metals. The asymmetry is more pronounced if one of the contact metals is aluminium. The asymmetry is lowest if one of the contact metals is silver and the other gold.

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The Packaging Research Center has been developing next generation system-on-a-package (SOP) technology with digital, RF, optical, and sensor functions integrated in a single package/module. The goal of this effort is to develop a platform substrate technology providing very high wiring density and embedded thin film passive and active components using PWB compatible materials and processes. The latest SOP baseline process test vehicle has been fabricated on novel Si-matched CTE, high modulus C-SiC composite core substrates using 10mum thick BCB dielectric films with loss tangent of 0.0008 and dielectric constant of 2.65. A semi-additive plating process has been developed for multilayer microvia build-up using BCB without the use of any vacuum deposition or polishing/CMP processes. PWB and package substrate compatible processes such as plasma surface treatment/desmear and electroless/electrolytic pulse reverse plating was used. The smallest line width and space demonstrated in this paper is 6mum with microvia diameters in the 15-30mum range. This build-up process has also been developed on medium CTE organic laminates including MCL-E-679F from Hitachi Chemical and PTFE laminates with Cu-Invar-Cu core. Embedded decoupling capacitors with capacitance density of >500nF/cm2 have been integrated into the build-up layers using sol-gel synthesized BaTiO3 thin films (200-300nm film thickness) deposited on copper foils and integrated using vacuum lamination and subtractive etch processes. Thin metal alloy resistor films have been integrated into the SOP substrate using two methods: (a) NiCrAlSi thin films (25ohms per square) deposited on copper foils (Gould Electronics) laminated on the build-up layers and two step etch process for resistor definition, and (b) electroless plated Ni-W-P thin films (70 ohms to few Kohms per square) on the BCB dielectric by plasma surface treatment and activation. The electrical design and build-up layer structure along- - with key materials and processes used in the fabrication of the SOP4 test vehicle were presented in this paper. Initial results from the high density wiring and embedded thin film components were also presented. The focus of this paper is on integration of materials, processes and structures in a single package substrate for system-on-a-package (SOP) implementation

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Gate driver is an integral part of every power converter, drives the power semiconductor devices and also provides protection for the switches against short-circuit events and over-voltages during shut down. Gate drive card for IGBTs and MOSFETs with basic features can be designed easily by making use of discrete electronic components. Gate driver ICs provides attractive features in a single package, which improves reliability and reduces effort of design engineers. Either case needs one or more isolated power supplies to drive each power semiconductor devices and provide isolation to the control circuitry from the power circuit. The primary emphasis is then to provide simplified and compact isolated power supplies to the gate drive card with the requisite isolation strength and which consumes less space, and for providing thermal protection to the power semiconductor modules for 3-� 3 wire or 4 wire inverters.

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This paper presents an experimental investigations performed on various electronic components used in telecommunication networks and those used in avionics for the ring wave surge voltages. IEEE Std C 62.41.1-2002 specifies a stringent requirement of waveforms to be applied for the evaluation of telecom components. To meet the necessary requirements in the absence of commercial equipment for generating the required waveforms, special efforts were made to fabricate a ring wave surge generator as per prescribed standards. The developed surge generator is capable of delivering an output of 0.5 mu s-100kHz which meets the requirements of telecom standards prescribed for evaluation of various modules used in low voltage ac power circuits used in communication networks. The results of the experimental investigations obtained on various modules used in communication networks are presented.

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As System-on-Chip (SoC) designs migrate to 28nm process node and beyond, the electromagnetic (EM) co-interactions of the Chip-Package-Printed Circuit Board (PCB) becomes critical and require accurate and efficient characterization and verification. In this paper a fast, scalable, and parallelized boundary element based integral EM solutions to Maxwell equations is presented. The accuracy of the full-wave formulation, for complete EM characterization, has been validated on both canonical structures and real-world 3-D system (viz. Chip + Package + PCB). Good correlation between numerical simulation and measurement has been achieved. A few examples of the applicability of the formulation to high speed digital and analog serial interfaces on a 45nm SoC are also presented.

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Two-dimensional magnetic recording (2-D TDMR) is an emerging technology that aims to achieve areal densities as high as 10 Tb/in(2) using sophisticated 2-D signal-processing algorithms. High areal densities are achieved by reducing the size of a bit to the order of the size of magnetic grains, resulting in severe 2-D intersymbol interference (ISI). Jitter noise due to irregular grain positions on the magnetic medium is more pronounced at these areal densities. Therefore, a viable read-channel architecture for TDMR requires 2-D signal-detection algorithms that can mitigate 2-D ISI and combat noise comprising jitter and electronic components. Partial response maximum likelihood (PRML) detection scheme allows controlled ISI as seen by the detector. With the controlled and reduced span of 2-D ISI, the PRML scheme overcomes practical difficulties such as Nyquist rate signaling required for full response 2-D equalization. As in the case of 1-D magnetic recording, jitter noise can be handled using a data-dependent noise-prediction (DDNP) filter bank within a 2-D signal-detection engine. The contributions of this paper are threefold: 1) we empirically study the jitter noise characteristics in TDMR as a function of grain density using a Voronoi-based granular media model; 2) we develop a 2-D DDNP algorithm to handle the media noise seen in TDMR; and 3) we also develop techniques to design 2-D separable and nonseparable targets for generalized partial response equalization for TDMR. This can be used along with a 2-D signal-detection algorithm. The DDNP algorithm is observed to give a 2.5 dB gain in SNR over uncoded data compared with the noise predictive maximum likelihood detection for the same choice of channel model parameters to achieve a channel bit density of 1.3 Tb/in(2) with media grain center-to-center distance of 10 nm. The DDNP algorithm is observed to give similar to 10% gain in areal density near 5 grains/bit. The proposed signal-processing framework can broadly scale to various TDMR realizations and areal density points.

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HeI photoelectron spectra of 1:1 electron donor-acceptor complexes are discussed in the light of molecular orbital calculations. The complexes discussed include those formed by BH3, BF3 and SO2. Some systematics have been found in the ionization energy shifts of the complexes compared to the free components and these are related to the strength of the donor-acceptor bond. Hel spectra of hydrogen bonded complexes are discussed in comparison with results from MO calculations. Limitations of such studies as well as scope for further investigations are indicated.

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Conjugated polymers are intensively pursued as candidate materials for emission and detection devices with the optical range of interest determined by the chemical structure. On the other hand the optical range for emission and detection can also be tuned by size selection in semiconductor nanoclusters. The mechanisms for charge generation and separation upon optical excitation, and light emission are different for these systems. Hybrid systems based on these different class of materials reveal interesting electronic and optical properties and add further insight into the individual characteristics of the different components. Multilayer structures and blends of these materials on different substrates were prepared for absorption, photocurrent (Iph), photoluminescence (PL) and electroluminscence (EL) studies. Polymers chosen were derivatives of polythiophene (PT) and polyparaphenylenevinylene (PPV) along with nanoclusters of cadmium sulphide of average size 4.4 nm (CdS-44). The photocurrent spectral response in these systems followed the absorption response around the band edges for each of the components and revealed additional features, which depended on bias voltage, thickness of the layers and interfacial effects. The current-voltage curves showed multi-component features with emission varying for different regimes of voltage. The emission spectral response revealed additive features and is discussed in terms of excitonic mechanisms.

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This paper analyses the influence of management on Technical Efficiency Change (TEC) and Technological Progress (TP) in the communication equipment and consumer electronics sub-sectors of Indian hardware electronics industry. Each sub-sector comprises 13 sample firms for two time periods.The primary objective is to determine the relative contribution of TP and TEC to TFP Growth (TFPG) and to establish the influence of firm specific operational management decision variables on these two components. The study finds that both the sub-sectors have strived and achieved steady TP but not TEC in the period of economic liberalisation to cope with the intensifying competition. The management decisions with respect to asset and profit utilization, vertical integration, among others, improved TP and TE in the sub-sectors. However, R&D investments and technology imports proved costly for TFP indicating inadequate efforts and/or poor resource utilisation by the management. Management was found to be complacent in terms of improving or developing their own technology as indicated by their higher dependence on import of raw materials and no influence of R&D on TP.

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Approximate calculations are reported on pyrene within the PPP model Hamiltonian using a novel restricted CI scheme which employs both molecular orbital and valence bond techniques. Also reported are detailed full CI results of the PPP model on 2,7-dihydropyrene obtained using the valence bond method. Spectral studies, charge and spin density calculations in ground and excited states, and ring current calculations in the ground state of the molecules are presented. In pyrene, the calculated excitation energies are in good agreement with experiment. The closed structure pi-conjugated molecule pyrene appears to show smaller distortions from the ground state geometry compared with the open structure pi-conjugated molecule 2,7-dihydropyrene. The ground state equilibrium structure of 2,7-dihydropyrene can be viewed as two hexatriene molecules connected by a vinyl crosslink, as is evident from bond order and ring current calculations. This is consistent with the only Kekule resonant structure possible for this molecule.

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By definition, the two faces of a pi bond are equivalent.1 However, they are rendered nonequivalent in most molecules because of the absence of a plane of symmetry encompassing the double bond and the adjacent substituents. As a result, additions to trigonal centers from the two faces need not be equally facile. Exploiting this stereodifferentiation in a controlled manner represents one of the core problems in organic synthesis. Evidently, the factors which determine such diastereoselection need to be delineated in as much detail as possible.

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The superconducting state of the cuprates in the presence of a magnetic field has been investigated very actively in the past few years through measurements of electrical and thermal transport, ac conductivity, specific heat, and other quantities. The observed behavior is not well understood; it probes the nature of quasiparticies, vortices, and their interactions in a superconductor with nodes in the pair amplitude. We summarize here experimental results and our attempts to understand the phenomena.