Programmable digital signal averager.

A high speed digital signal averager with programmable features for the sampling period, for the number of channels and for the number of sweeps is described. The system implements a stable averaging algorithm (Deadroff and Trimble 1968) to provide a stable, calibrated display. The performance of the instrument has been evaluated for the reduction of random noise and for comb-filter action. Special uses of the instrument as a box-car integrator and as a transient recorder are also indicated.

Comments and Correspondence on a programmable digital signal averager

In a recent paper, Srinivasan et al (1980) have described a programmable digital signal averager with facility for programming the sampling period, number of channels and number of sweeps. We have examined this paper in some detail and find that some points need clarification.

'A programmable digital signal averager' Reply

In a recent paper, Srinivasan et al (1980) have described a programmable digital signal averager with facility for programming the sampling period, number of channels and number of sweeps. We have examined this paper in some detail and find that some points need clarification.

On a programmable signal processor for VLSI

This paper presents a method of designing a programmable signal processor based on a bit parallel matrix vector matrix multiplier (linear transformer). The salient feature of this design is that the efficiency of the direct vector matrix multiplier is improved and VLSI design is made much simpler by trading off the more expensive arithematic operation (multiplication) for 'cheaper' manipulation (addition/subtraction) of the data.

Robust flight stability and control for micro air vehicles.

This chapter presents the real time validation of fixed order robust 112 controller designed for the lateral stabilisation of a micro air vehicle named Sarika2. Digital signal processor (DSP) based onboard computer named flight instrumentation controller (FIC) is designed to operate under automatic or manual mode. FIC gathers data from multitude of sensors and is capable of closed loop control to enable autonomous flight. Fixed order lateral H-2 controller designed with the features such as incorporation of level I flying qualities, gust alleviation and noise rejection is coded on to the FIC. Challenging real time hardware in loop simulation (HILS) is done with dSPACE1104 RTI/RTW. Responses obtained from the HILS are compared with those obtained from the offline simulation. Finally, flight trials are conducted to demonstrate the satisfactory performance of the closed loop system. The generic design methodology developed is applicable to all classes of Mini and Micro air vehicles.

A voltage-sensorless control method to balance the input currents of a three-wire boost rectifier under unbalanced input voltages condition

This paper proposes a control method that can balance the input currents of the three-phase three-wire boost rectifier under unbalanced input voltage condition. The control objective is to operate the rectifier in the high-power-factor mode under balanced input voltage condition but to give overriding priority to the current balance function in case of unbalance in the input voltage. The control structure has been divided into two major functional blocks. The inner loop current-mode controller implements resistor emulation to achieve high-power-factor operation on each of the two orthogonal axes of the stationary reference frame. The outer control loop performs magnitude scaling and phase-shifting operations on current of one of the axes to make it balanced with the current on the other axis. The coefficients of scaling and shifting functions are determined by two closed-loop prportional-integral (PI) controllers that impose the conditions of input current balance as PI references. The control algorithm is simple and high performing. It does not require input voltage sensing and transformation of the control variables into a rotating reference frame. The simulation results on a MATLAB-SIMULINK platform validate the proposed control strategy. In implementation Texas Instrument's digital signal processor TMS320F24OF is used as the digital controller. The control algorithm for high-power-factor operation is tested on a prototype boost rectifier under nominal and unbalanced input voltage conditions.

Grid interfacing of a photovoltaic system using a chain cell converter

With the rapid development of photovoltaic system installations and increased number of grid connected power systems, it has become imperative to develop an efficient grid interfacing instrumentation suitable for photovoltaic systems ensuring maximum power transfer. The losses in the power converter play an important role in the overall efficiency of a PV system. Chain cell converter is considered to be efficient as compared to PWM converters due to lower switching losses, modularized circuit layout, reduced voltage rating of the converter switches, reduced EMI. The structure of separate dc sources in chain cell converter is well suited for photovoltaic systems as there will b several separate PV modules in the PV array which can act as an individual dc source. In this work, a single phase multilevel chain cell converter is used to interface the photovoltaic array to a single phase grid at a frequency of 50Hz. Control algorithms are developed for efficient interfacing of the PV system with grid and isolating the PV system from grid under faulty conditions. Digital signal processor TMS320F 2812 is used to implement the control algorithms developed and for the generation of other control signals.

A method of tracking the peak power points for a variable speed wind energy conversion system

In this paper, a method of tracking the peak power in a wind energy conversion system (WECS) is proposed, which is independent of the turbine parameters and air density. The algorithm searches for the peak power by varying the speed in the desired direction. The generator is operated in the speed control mode with the speed reference being dynamically modified in accordance with the magnitude and direction of change of active power. The peak power points in the P-omega curve correspond to dP/domega = 0. This fact is made use of in the optimum point search algorithm. The generator considered is a wound rotor induction machine whose stator is connected directly to the grid and the rotor is fed through back-to-back pulse-width-modulation (PWM) converters. Stator flux-oriented vector control is applied to control the active and reactive current loops independently. The turbine characteristics are generated by a dc motor fed from a commercial dc drive. All of the control loops are executed by a single-chip digital signal processor (DSP) controller TMS320F240. Experimental results show that the performance of the control algorithm compares well with the conventional torque control method.

Nearly Constant Switching Frequency Hysteresis Current Controller with Fast Online Computation of Boundary for a 2-Level Induction Motor Drive

A nearly constant switching frequency current hysteresis controller for a 2-level inverter fed induction motor drive is proposed in this paper: The salient features of this controller are fast dynamics for the current, inherent protection against overloads and less switching frequency variation. The large variation of switching frequency as in the conventional hysteresis controller is avoided by defining a current-error boundary which is obtained from the current-error trajectory of the standard space vector PWM. The current-error boundary is computed at every sampling interval based on the induction machine parameters and from the estimated fundamental stator voltage. The stator currents are always monitored and when the current-error exceeds the boundary, voltage space vector is switched to reduce the current-error. The proposed boundary computation algorithm is applicable in linear and over-modulation region and it is simple to implement in any standard digital signal processor: Detailed experimental verification is done using a 7.5 kW induction motor and the results are given to show the performance of the drive at various operating conditions and validate the proposed advantages.

A Real-time clustering system for spatio-temporal signals from network of neurons

Over past few years, the studies of cultured neuronal networks have opened up avenues for understanding the ion channels, receptor molecules, and synaptic plasticity that may form the basis of learning and memory. The hippocampal neurons from rats are dissociated and cultured on a surface containing a grid of 64 electrodes. The signals from these 64 electrodes are acquired using a fast data acquisition system MED64 (Alpha MED Sciences, Japan) at a sampling rate of 20 K samples with a precision of 16-bits per sample. A few minutes of acquired data runs in to a few hundreds of Mega Bytes. The data processing for the neural analysis is highly compute-intensive because the volume of data is huge. The major processing requirements are noise removal, pattern recovery, pattern matching, clustering and so on. In order to interface a neuronal colony to a physical world, these computations need to be performed in real-time. A single processor such as a desk top computer may not be adequate to meet this computational requirements. Parallel computing is a method used to satisfy the real-time computational requirements of a neuronal system that interacts with an external world while increasing the flexibility and scalability of the application. In this work, we developed a parallel neuronal system using a multi-node Digital Signal processing system. With 8 processors, the system is able to compute and map incoming signals segmented over a period of 200 ms in to an action in a trained cluster system in real time.

Narrowband signal detection techniques in shallow ocean by acoustic vector sensor array

This paper presents the formulation and performance analysis of four techniques for detection of a narrowband acoustic source in a shallow range-independent ocean using an acoustic vector sensor (AVS) array. The array signal vector is not known due to the unknown location of the source. Hence all detectors are based on a generalized likelihood ratio test (GLRT) which involves estimation of the array signal vector. One non-parametric and three parametric (model-based) signal estimators are presented. It is shown that there is a strong correlation between the detector performance and the mean-square signal estimation error. Theoretical expressions for probability of false alarm and probability of detection are derived for all the detectors, and the theoretical predictions are compared with simulation results. It is shown that the detection performance of an AVS array with a certain number of sensors is equal to or slightly better than that of a conventional acoustic pressure sensor array with thrice as many sensors.

An Unbiased Risk Estimator for Multiplicative Noise - Application to 1-D Signal Denoising

The effect of multiplicative noise on a signal when compared with that of additive noise is very large. In this paper, we address the problem of suppressing multiplicative noise in one-dimensional signals. To deal with signals that are corrupted with multiplicative noise, we propose a denoising algorithm based on minimization of an unbiased estimator (MURE) of meansquare error (MSE). We derive an expression for an unbiased estimate of the MSE. The proposed denoising is carried out in wavelet domain (soft thresholding) by considering time-domain MURE. The parameters of thresholding function are obtained by minimizing the unbiased estimator MURE. We show that the parameters for optimal MURE are very close to the optimal parameters considering the oracle MSE. Experiments show that the SNR improvement for the proposed denoising algorithm is competitive with a state-of-the-art method.

Reduced complexity two stage vector quantization

We address the issue of complexity for vector quantization (VQ) of wide-band speech LSF (line spectrum frequency) parameters. The recently proposed switched split VQ (SSVQ) method provides better rate-distortion (R/D) performance than the traditional split VQ (SVQ) method, even at the requirement of lower computational complexity. but at the expense of much higher memory. We develop the two stage SVQ (TsSVQ) method, by which we gain both the memory and computational advantages and still retain good R/D performance. The proposed TsSVQ method uses a full dimensional quantizer in its first stage for exploiting all the higher dimensional coding advantages and then, uses an SVQ method for quantizing the residual vector in the second stage so as to reduce the complexity. We also develop a transform domain residual coding method in this two stage architecture such that it further reduces the computational complexity. To design an effective residual codebook in the second stage, variance normalization of Voronoi regions is carried out which leads to the design of two new methods, referred to as normalized two stage SVQ (NTsSVQ) and normalized two stage transform domain SVQ (NTsTrSVQ). These two new methods have complimentary strengths and hence, they are combined in a switched VQ mode which leads to the further improvement in R/D performance, but retaining the low complexity requirement. We evaluate the performances of new methods for wide-band speech LSF parameter quantization and show their advantages over established SVQ and SSVQ methods.

Asymmetric cross-coupled differential pair configuration to realize neuron activation function and its derivative

In this brief, we present a new circuit technique to generate the sigmoid neuron activation function (NAF) and its derivative (DNAF). The circuit makes use of transistor asymmetry in cross-coupled differential pair to obtain the derivative. The asymmetry is introduced through external control signal, as and when required. This results in the efficient utilization of the hard-ware by realizing NAF and DNAF using the same building blocks. The operation of the circuit is presented in the subthreshold region for ultra low-power applications. The proposed circuit has been experimentally prototyped and characterized as a proof of concept on the 1.5-mum AMI technology.