An efficient reduction algorithm for computation of interconnect delay variability for statistical timing analysis in clock tree planning

In this paper, we propose a novel and efficient algorithm for modelling sub-65 nm clock interconnect-networks in the presence of process variation. We develop a method for delay analysis of interconnects considering the impact of Gaussian metal process variations. The resistance and capacitance of a distributed RC line are expressed as correlated Gaussian random variables which are then used to compute the standard deviation of delay Probability Distribution Function (PDF) at all nodes in the interconnect network. Main objective is to find delay PDF at a cheaper cost. Convergence of this approach is in probability distribution but not in mean of delay. We validate our approach against SPICE based Monte Carlo simulations while the current method entails significantly lower computational cost.

Ignition delay studies on hydrocarbon fuel with and without additives

Single pulse shock tube facility has been developed in the High Temperature Chemical Kinetics Lab, Aerospace Engineering Department, to carry out ignition delay studies and spectroscopic investigations of hydrocarbon fuels. Our main emphasis is on measuring ignition delay through pressure rise and by monitoring CH emission for various jet fuels and finding suitable additives for reducing the delay. Initially the shock tube was tested and calibrated by measuring the ignition delay of C2H6-O2 mixture. The results are in good agreement with earlier published works. Ignition times of exo-tetrahdyrodicyclopentadiene (C10H16), which is a leading candidate fuel for scramjet propulsion has been studied in the reflected shock region in the temperature range 1250 - 1750 K with and without adding Triethylamine (TEA). Addition of TEA results in substantial reduction of ignition delay of C10H16.

Single-Generation Network Coding for Networks with Delay

A single-source network is said to be memory-free if all of the internal nodes (those except the source and the sinks) do not employ memory but merely send linear combinations of the incoming symbols (received at their incoming edges) on their outgoing edges. Memory-free networks with delay using network coding are forced to do inter-generation network coding, as a result of which the problem of some or all sinks requiring a large amount of memory for decoding is faced. In this work, we address this problem by utilizing memory elements at the internal nodes of the network also, which results in the reduction of the number of memory elements used at the sinks. We give an algorithm which employs memory at all the nodes of the network to achieve single- generation network coding. For fixed latency, our algorithm reduces the total number of memory elements used in the network to achieve single- generation network coding. We also discuss the advantages of employing single-generation network coding together with convolutional network-error correction codes (CNECCs) for networks with unit- delay and illustrate the performance gain of CNECCs by using memory at the intermediate nodes using simulations on an example network under a probabilistic network error model.

Multiple scales without center manifold reductions for delay differential equations near Hopf bifurcations

We study small perturbations of three linear Delay Differential Equations (DDEs) close to Hopf bifurcation points. In analytical treatments of such equations, many authors recommend a center manifold reduction as a first step. We demonstrate that the method of multiple scales, on simply discarding the infinitely many exponentially decaying components of the complementary solutions obtained at each stage of the approximation, can bypass the explicit center manifold calculation. Analytical approximations obtained for the DDEs studied closely match numerical solutions.

Energy Reduction in SRAM using Dynamic Voltage and Frequency Management

This paper describes a dynamic voltage frequency control scheme for a 256 X 64 SRAM block for reducing the energy in active mode and stand-by mode. The DVFM control system monitors the external clock and changes the supply voltage and the body bias so as to achieve a significant reduction in energy. The behavioral model of the proposed DVFM control system algorithm is described and simulated in HDL using delay and energy parameters obtained through SPICE simulation. The frequency range dictated by an external controller is 100 MHz to I GHz. The supply voltage of the complete memory system is varied in steps of 50 mV over the range of 500 mV to IV. The threshold voltage range of operation is plusmn100 mV around the nominal value, achieving 83.4% energy reduction in the active mode and 86.7% in the stand-by mode. This paper also proposes a energy replica that is used in the energy monitor subsystem of the DVFM system.

Voltage and Temperature-Aware SSTA Using Neural Network Delay Model

With the emergence of voltage scaling as one of the most powerful power reduction techniques, it has been important to support voltage scalable statistical static timing analysis (SSTA) in deep submicrometer process nodes. In this paper, we propose a single delay model of logic gate using neural network which comprehensively captures process, voltage, and temperature variation along with input slew and output load. The number of simulation programs with integrated circuit emphasis (SPICE) required to create this model over a large voltage and temperature range is found to be modest and 4x less than that required for a conventional table-based approach with comparable accuracy. We show how the model can be used to derive sensitivities required for linear SSTA for an arbitrary voltage and temperature. Our experimentation on ISCAS 85 benchmarks across a voltage range of 0.9-1.1V shows that the average error in mean delay is less than 1.08% and average error in standard deviation is less than 2.85%. The errors in predicting the 99% and 1% probability point are 1.31% and 1%, respectively, with respect to SPICE. The two potential applications of voltage-aware SSTA have been presented, i.e., one for improving the accuracy of timing analysis by considering instance-specific voltage drops in power grids and the other for determining optimum supply voltage for target yield for dynamic voltage scaling applications.

Time delay to firing of a triggered vacuum gap with barium titanate in trigger gap

The time delay to the firing of a triggered vacuum gap (t.v.g.) containing barium titanate in the trigger gap is investigated as a function of the main gap voltage, main gap length, trigger pulse duration, trigger current and trigger voltage. The time delay decreases steadily with increasing trigger current and trigger voltage until it reaches saturation. The effect of varying the main gap length and voltage on the time delay is not strong. Before `conditioning�¿ the t.v.g. two groups of time delays, long (>100�¿s) and short (<10�¿s), are simultaneously observed when a large number of trials are conducted. After conditioning, only the group of short time delays are present. This is attributed to the marked reduction of the resistance of the trigger gap across the surface of the solid dielectric resulting directly from the conditioning effect.

Frequency domain turbo equalization for MIMO-CPSC systems with large delay spreads

In this paper, we consider low-complexity turbo equalization for multiple-input multiple-output (MIMO) cyclic prefixed single carrier (CPSC) systems in MIMO inter-symbol interference (ISI) channels characterized by large delay spreads. A low-complexity graph based equalization is carried out in the frequency domain. Because of the reduction in correlation among the noise samples that happens for large frame sizes and delay spreads in frequency domain processing, improved performance compared to time domain processing is shown to be achieved. This improved performance is attractive for equalization in severely delay spread ISI channels like ultrawideband channels and underwater acoustic channels.

A provably tight delay-driven concurrently congestion mitigating global routing algorithm

Routing is a very important step in VLSI physical design. A set of nets are routed under delay and resource constraints in multi-net global routing. In this paper a delay-driven congestion-aware global routing algorithm is developed, which is a heuristic based method to solve a multi-objective NP-hard optimization problem. The proposed delay-driven Steiner tree construction method is of O(n(2) log n) complexity, where n is the number of terminal points and it provides n-approximation solution of the critical time minimization problem for a certain class of grid graphs. The existing timing-driven method (Hu and Sapatnekar, 2002) has a complexity O(n(4)) and is implemented on nets with small number of sinks. Next we propose a FPTAS Gradient algorithm for minimizing the total overflow. This is a concurrent approach considering all the nets simultaneously contrary to the existing approaches of sequential rip-up and reroute. The algorithms are implemented on ISPD98 derived benchmarks and the drastic reduction of overflow is observed. (C) 2014 Elsevier Inc. All rights reserved.

Within-Die Gate Delay Variability Measurement using Re-configurable Ring Oscillator

We report a circuit technique to measure the on-chip delay of an individual logic gate (both inverting and non-inverting) in its unmodified form using digitally reconfigurable ring oscillator (RO). Solving a system of linear equations with different configuration setting of the RO gives delay of an individual gate. Experimental results from a test chip in 65nm process node show the feasibility of measuring the delay of an individual inverter to within 1pS accuracy. Delay measurements of different nominally identical inverters in close physical proximity show variations of up to 26% indicating the large impact of local or within-die variations.

Infinite Dimensional Slow Modulations In A Delayed Model For Orthogonal Cutting Vibrations

We apply the method of multiple scales (MMS) to a well known model of regenerative cutting vibrations in the large delay regime. By ``large'' we mean the delay is much larger than the time scale of typical cutting tool oscillations. The MMS upto second order for such systems has been developed recently, and is applied here to study tool dynamics in the large delay regime. The second order analysis is found to be much more accurate than first order analysis. Numerical integration of the MMS slow flow is much faster than for the original equation, yet shows excellent accuracy. The main advantage of the present analysis is that infinite dimensional dynamics is retained in the slow flow, while the more usual center manifold reduction gives a planar phase space. Lower-dimensional dynamical features, such as Hopf bifurcations and families of periodic solutions, are also captured by the MMS. Finally, the strong sensitivity of the dynamics to small changes in parameter values is seen clearly.

High Oxygen Storage Capacity and High Rates of CO Oxidation and NO Reduction Catalytic Properties of Ce1-xSnxO2 and Ce0.78Sn0.2Pd0.02O2-delta

Ce1-xSnxO2 (x = 0.1-0.5) solid solution and its Pd substituted analogue have been prepared by a single step solution combustion method using tin oxalate precursor. The compounds were characterized by X-ray diffraction (XRD), X-ray photoelectron spectroscopy (XPS), transmission electron microscopy (TEM), and H-2/temperature programmed redution (TPR) studies. The cubic fluorite structure remained intact up to 50% of Sri substitution in CeO2, and the compounds were stable up to 700 C. Oxygen storage capacity of Ce1-xSnxO2 was found to be much higher than that of Ce1-xZrxO2 due to accessible Ce4+/Ce3+ and Sn4+/Sn2+ redox couples at temperatures between 200 and 400 C. Pd 21 ions in Ce0.78Sn0.2Pd0.02O2-delta are highly ionic, and the lattice oxygen of this catalyst is highly labile, leading to low temperature CO to CO2 conversion. The rate of CO oxidation was 2 mu mol g(-1) s(-1) at 50 degrees C. NO reduction by CO with 70% N-2 selectivity was observed at similar to 200 degrees C and 100% N-2 selectivity below 260 degrees C with 1000-5000 ppm NO. Thus, Pd2+ ion substituted Ce1-xSnxO2 is a superior catalyst compared to Pd2+ ions in CeO2, Ce1-xZrxO2, and Ce1-xTixO2 for low temperature exhaust applications due to the involvement of the Sn2+/Sn4+ redox couple along with Pd2+/Pd-0 and Ce4+/Ce3+ couples.

Studies in metal-ammonia reduction-5: Reduction and reductive methylation of some naphthoic acids

Birch reductio and reductive methylations of some substituted naphtholic acids have been examined. The factors influencing the mechanism of reduction process have been discussed. Some of the reduced naphthoic acids are useful synthons for synthesis.

Calciothermic reduction of TiO2: A diagrammatic assessment of the thermodynamic limit of deoxidation

Calciothermic reduction of TiO2 provides a potentially low-cost route to titanium production. Presented in this article is a suitably designed diagram, useful for assessing the degree of reduction of TiO2 and residual oxygen contamination in metal as a function of reduction temperature and other process parameters. The oxygen chemical potential diagram à la Ellingham-Richardson-Jeffes is useful for visualization of the thermodynamics of reduction reactions at high temperatures. Although traditionally the diagram depicts oxygen potentials corresponding to the oxidation of different metals to their corresponding oxides or of lower oxides to higher oxides, oxygen potentials associated with solution phases at constant composition can be readily superimposed. The usefulness of the diagram for an insightful analysis of calciothermic reduction, either direct or through an electrochemical process, is discussed. Identified are possible process variations, modeling and optimization strategies.