Magnetic trapping of Yb in the metastable P-3(2) state

We report magnetic trapping of Yb in the excited P-3(2) state. This state, with a lifetime of 15 s, could play an important role in studies ranging from optical clocks and quantum computation to the search for a permanent electric dipole moment. Yb atoms are first cooled and trapped in the ground state in a 399-nm magneto-optic trap. The cold atoms are then pumped into the excited state by driving the S-1(0) -> P-3(1) -> S-3(1) transition. Atoms in the P-3(2) state are magnetically trapped in a spherical quadrupole field with an axial gradient of 110 G/cm. We trap up to 10(6) atoms with a lifetime of 1.5 s.

0.84 ps Resolution Clock Skew Measurement via Subsampling

An all-digital on-chip clock skew measurement system via subsampling is presented. The clock nodes are sub-sampled with a near-frequency asynchronous sampling clock to result in beat signals which are themselves skewed in the same proportion but on a larger time scale. The beat signals are then suitably masked to extract only the skews of the rising edges of the clock signals. We propose a histogram of the arithmetic difference of the beat signals which decouples the relationship of clock jitter to the minimum measurable skew, and allows skews arbitrarily close to zero to be measured with a precision limited largely by measurement time, unlike the conventional XOR based histogram approach. We also analytically show that the proposed approach leads to an unbiased estimate of skew. The measured results from a 65 nm delay measurement front-end indicate that for an input skew range of +/- 1 fan-out-of-4 (FO4) delay, +/- 3 sigma resolution of 0.84 ps can be obtained with an integral error of 0.65 ps. We also experimentally demonstrate that a frequency modulation on a sampling clock maintains precision, indicating the robustness of the technique to jitter. We also show how FM modulation helps in restoring precision in case of rationally related clocks.

A weighted average-based external clock synchronisation protocol for wireless sensor networks

Wireless Sensor Networks (WSNs) have many application scenarios where external clock synchronisation may be required because a WSN may consist of components which are not connected to each other. In this paper, we first propose a novel weighted average-based internal clock synchronisation (WICS) protocol, which synchronises all the clocks of a WSN with the clock of a reference node periodically. Based on this protocol, we then propose our weighted average-based external clock synchronisation (WECS) protocol. We have analysed the proposed protocols for maximum synchronisation error and shown that it is always upper bounded. Extensive simulation studies of the proposed protocols have been carried out using Castalia simulator. Simulation results validate our above theoretical claim and also show that the proposed protocols perform better in comparison to other protocols in terms of synchronisation accuracy. A prototype implementation of the WICS protocol using a few TelosB motes also validates the above conclusions.

Design and analysis of a peer-to-peer based distributed clock synchronisation protocol for wireless sensor networks

Clock synchronisation is an important requirement for various applications in wireless sensor networks (WSNs). Most of the existing clock synchronisation protocols for WSNs use some hierarchical structure that introduces an extra overhead due to the dynamic nature of WSNs. Besides, it is difficult to integrate these clock synchronisation protocols with sleep scheduling scheme, which is a major technique to conserve energy. In this paper, we propose a fully distributed peer-to-peer based clock synchronisation protocol, named Distributed Clock Synchronisation Protocol (DCSP), using a novel technique of pullback for complete sensor networks. The pullback technique ensures that synchronisation phases of any pair of clocks always overlap. We have derived an exact expression for a bound on maximum synchronisation error in the DCSP protocol, and simulation study verifies that it is indeed less than the computed upper bound. Experimental study using a few TelosB motes also verifies that the pullback occurs as predicted.

A weighted average based external clock synchronization protocol for wireless sensor networks

Clock synchronization is an extremely important requirement of wireless sensor networks(WSNs). There are many application scenarios such as weather monitoring and forecasting etc. where external clock synchronization may be required because WSN itself may consists of components which are not connected to each other. A usual approach for external clock synchronization in WSNs is to synchronize the clock of a reference node with an external source such as UTC, and the remaining nodes synchronize with the reference node using an internal clock synchronization protocol. In order to provide highly accurate time, both the offset and the drift rate of each clock with respect to reference node are estimated from time to time, and these are used for getting correct time from local clock reading. A problem with this approach is that it is difficult to estimate the offset of a clock with respect to the reference node when drift rate of clocks varies over a period of time. In this paper, we first propose a novel internal clock synchronization protocol based on weighted averaging technique, which synchronizes all the clocks of a WSN to a reference node periodically. We call this protocol weighted average based internal clock synchronization(WICS) protocol. Based on this protocol, we then propose our weighted average based external clock synchronization(WECS) protocol. We have analyzed the proposed protocols for maximum synchronization error and shown that it is always upper bounded. Extensive simulation studies of the proposed protocols have been carried out using Castalia simulator. Simulation results validate our theoretical claim that the maximum synchronization error is always upper bounded and also show that the proposed protocols perform better in comparison to other protocols in terms of synchronization accuracy. A prototype implementation of the proposed internal clock synchronization protocol using a few TelosB motes also validates our claim.

Rhythmic egg-laying behaviour in virgin females of fruit flies Drosophila melanogaster

Fruit fly Drosophila melanogaster females display rhythmic egg-laying under 12: 12 h light/dark (LD) cycles which persists with near 24 h periodicity under constant darkness (DD). We have shown previously that persistence of this rhythm does not require the neurons expressing pigment dispersing factor (PDF), thought to be the canonical circadian pacemakers, and proposed that it could be controlled by peripheral clocks or regulated/triggered by the act of mating. We assayed egg-laying behaviour of wild-type Canton S (CS) females under LD, DD and constant light (LL) conditions in three different physiological states; as virgins, as females allowed to mate with males for 1 day and as females allowed to mate for the entire duration of the assay. Here, we report the presence of a circadian rhythm in egg-laying in virgin D. melanogaster females. We also found that egg-laying behaviour of 70 and 90% females from all the three male presence/absence protocols follows circadian rhythmicity under DD and LL, with periods ranging between 18 and 30 h. The egg-laying rhythm of all virgin females synchronized to LD cycles with a peak occurring soon after lights-off. The rhythm in virgins was remarkably robust with maximum number of eggs deposited immediately after lights-off in contrast to mated females which show higher egg-laying during the day. These results suggest that the egg-laying rhythm of D. melanogaster is endogenously driven and is neither regulated nor triggered by the act of mating; instead, the presence of males results in reduction in entrainment to LD cycles.