A systems approach to rural housing

An attempt is made in this paper to arrive at a methodology for generating building technologies appropriate to rural housing. An evaluation of traditional modern' technologies currently in use reveals the need for alternatives. The lacunae in the presently available technologies also lead to a definition of rural housing needs. It is emphasised that contending technologies must establish a 'goodness of fit' between the house form and the pattern of needs. A systems viewpoint which looks at the dynamic process of building construction and the static structure of the building is then suggested as a means to match the technologies to the needs. The process viewpoint emphasises the role of building materials production and transportation in achieving desired building performances. A couple of examples of technological alternatives like the compacted soil block and the polythene-stabilised soil roof covering are then discussed. The static structural system viewpoint is then studied to arrive at methodologies of cost reduction. An illustrative analysis is carried out using the dynamic programming technique, to arrive at combinations of alternatives for the building components which lead to cost reduction. Some of the technological options are then evaluated against the need patterns. Finally, a guideline for developments in building technology is suggested

Design and realization of high-performance wave-pipelined 8×8 b multiplier in CMOS technology

Wave pipelining is a design technique for increasing the throughput of a digital circuit or system without introducing pipelining registers between adjacent combinational logic blocks in the circuit/system. However, this requires balancing of the delays along all the paths from the input to the output which comes the way of its implementation. Static CMOS is inherently susceptible to delay variation with input data, and hence, receives a low priority for wave pipelined digital design. On the other hand, ECL and CML, which are amenable to wave pipelining, lack the compactness and low power attributes of CMOS. In this paper we attempt to exploit wave pipelining in CMOS technology. We use a single generic building block in Normal Process Complementary Pass Transistor Logic (NPCPL), modeled after CPL, to achieve equal delay along all the propagation paths in the logic structure. An 8×8 b multiplier is designed using this logic in a 0.8 ?m technology. The carry-save multiplier architecture is modified suitably to support wave pipelining, viz., the logic depth of all the paths are made identical. The 1 mm×0.6 mm multiplier core supports a throughput of 400 MHz and dissipates a total power of 0.6 W. We develop simple enhancements to the NPCPL building blocks that allow the multiplier to sustain throughputs in excess of 600 MHz. The methodology can be extended to introduce wave pipelining in other circuits as well