Analytical Field-Effect Method for Extraction of Subgap States in Thin-Film Transistors

We present an analytical field-effect method to extract the density of subgap states (subgap DOS) in amorphous semiconductor thin-film transistors (TFTs), using a closed-form relationship between surface potential and gate voltage. By accounting the interface states in the subthreshold characteristics, the subgap DOS is retrieved, leading to a reasonably accurate description of field-effect mobility and its gate voltage dependence. The method proposed here is very useful not only in extracting device performance but also in physically based compact TFT modeling for circuit simulation.

AIM-Spice Integration of a Recursive Model for Threshold Voltage Shift in Thin Film Transistors

Non-crystalline semiconductor based thin film transistors are the building blocks of large area electronic systems. These devices experience a threshold voltage shift with time due to prolonged gate bias stress. In this paper we integrate a recursive model for threshold voltage shift with the open source BSIM4V4 model of AIM-Spice. This creates a tool for circuit simulation for TFTs. We demonstrate the integrity of the model using several test cases including display driver circuits.

Fourier spectrum based extraction of an equivalent trap state density in indium gallium zinc oxide transistors

Segregating the dynamics of gate bias induced threshold voltage shift, and in particular, charge trapping in thin film transistors (TFTs) based on time constants provides insight into the different mechanisms underlying TFTs instability. In this Letter we develop a representation of the time constants and model the magnitude of charge trapped in the form of an equivalent density of created trap states. This representation is extracted from the Fourier spectrum of the dynamics of charge trapping. Using amorphous In-Ga-Zn-O TFTs as an example, the charge trapping was modeled within an energy range of Delta E-t approximate to 0.3 eV and with a density of state distribution as D-t(Et-j) = D-t0 exp(-Delta E-t/kT) with D-t0 = 5.02 x 10(11) cm(-2) eV(-1). Such a model is useful for developing simulation tools for circuit design. (C) 2014 AIP Publishing LLC.

Influence of curvature on the device physics of thin film transistors on flexible substrates

Thin film transistors (TFTs) on elastomers promise flexible electronics with stretching and bending. Recently, there have been several experimental studies reporting the behavior of TFTs under bending and buckling. In the presence of stress, the insulator capacitance is influenced due to two reasons. The first is the variation in insulator thickness depending on the Poisson ratio and strain. The second is the geometric influence of the curvature of the insulator-semiconductor interface during bending or buckling. This paper models the role of curvature on TFT performance and brings to light an elegant result wherein the TFT characteristics is dependent on the area under the capacitance-distance curve. The paper compares models with simulations and explains several experimental findings reported in literature. (C) 2014 AIP Publishing LLC.

Instability in an amorphous In-Ga-Zn-O field effect transistor upon water exposure

The instability of an amorphous indium-gallium-zinc oxide (IGZO) field effect transistor is investigated upon water treatment. Electrical characteristics are measured before, immediately after and a few days after water treatment in ambient as well as in vacuum conditions. It is observed that after a few days of water exposure an IGZO field effect transistor (FET) shows relatively more stable behaviour as compared to before exposure. Transfer characteristics are found to shift negatively after immediate water exposure and in vacuum. More interestingly, after water exposure the off current is found to decrease by 1-2 orders of magnitude and remains stable even after 15 d of water exposure in ambient as well as in vacuum, whereas the on current more or less remains the same. An x-ray photoelectron spectroscopic study is carried out to investigate the qualitative and quantitative analysis of IGZO upon water exposure. The changes in the FET parameters are evaluated and attributed to the formation of excess oxygen vacancies and changes in the electronic structure of the IGZO bulk channel and at the IGZO/SiO2 interface, which can further lead to the formation of subgap states. An attempt is made to distinguish which parameters of the FET are affected by the changes in the electronic structure of the IGZO bulk channel and at the IGZO/SiO2 interface separately.

Design Optimization of Thin-Film Transistors Based on a Metal-Substrate-Semiconductor Architecture for High DC Voltage Sensing

We discuss the potential application of high dc voltage sensing using thin-film transistors (TFTs) on flexible substrates. High voltage sensing has potential applications for power transmission instrumentation. For this, we consider a gate metal-substrate-semiconductor architecture for TFTs. In this architecture, the flexible substrate not only provides mechanical support but also plays the role of the gate dielectric of the TFT. Hence, the thickness of the substrate needs to be optimized for maximizing transconductance, minimizing mechanical stress, and minimizing gate leakage currents. We discuss this optimization, and develop n-type and p-type organic TFTs using polyvinyldene fluoride as the substrate-gate insulator. Circuits are also realized to achieve level shifting, amplification, and high drain voltage operation.