Worst-Case Asymmetric Distributed Source Coding

We consider the asymmetric distributed source coding problem, where the recipient interactively communicates with N correlated informants to gather their data. We are mainly interested in minimizing the worst-case number of informant bits required for successful data-gathering at recipient, but we are also concerned with minimizing the number of rounds as well as the number of recipient bits. We provide two algorithms, one that optimally minimizes the number of informant bits and other that trades-off the number of informant bits to efficiently reduce the number of rounds and number of recipient bits.

Performance and variability trade-off with gate-to-source/drain overlap length

The impact of gate-to-source/drain overlap length on performance and variability of 65 nm CMOS is presented. The device and circuit variability is investigated as a function of three significant process parameters, namely gate length, gate oxide thickness, and halo dose. The comparison is made with three different values of gate-to-source/drain overlap length namely 5 nm, 0 nm, and -5 nm and at two different leakage currents of 10 nA and 100 nA. The Worst-Case-Analysis approach is used to study the inverter delay fluctuations at the process corners. The drive current of the device for device robustness and stage delay of an inverter for circuit robustness are taken as performance metrics. The design trade-off between performance and variability is demonstrated both at the device level and circuit level. It is shown that larger overlap length leads to better performance, while smaller overlap length results in better variability. Performance trades with variability as overlap length is varied. An optimal value of overlap length of 0 nm is recommended at 65 nm gate length, for a reasonable combination of performance and variability.