99 resultados para Testing-machines

em Indian Institute of Science - Bangalore - Índia


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Among the multitude of test specimen geometries used for dynamic fiacture toughness evaluation, the most widely uscd specimen is lhc Chavpy specimen due its simple geomclry and availability of testing machines. The standard Chatpy specimen dimensions may llOl always give plane st~ain condilions and hence, it may be necessary Io coilduct lcs/s using specimens of dillEvcnt thicknesses to establish the plane strain K~a. An axisymmct/ic specimen, on the otlaev hand would always give flow constraints l~n a nominal specimen thickness i~rcspcctive of the test matctial. The notched disk specimen pVOl)oscd by Bcrn:ud ctal. [1] for static and dynamic initiation toughness measurement although p~ovicles plain-strain conditions, the crack plopagatcs at an angle to the direction of applied load. This makes inteq~retation of the test results difficult us it ~Ccluivcs ~actial slices to be cut fiom the fractured specimen to ascertain the angle o1 crack growth and a linite element model l~)r tl);t{ pa~ticulat ctack o~icntalion.

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We study the problem of minimizing total completion time on single and parallel batch processing machines. A batch processing machine is one which can process up to B jobs simultaneously. The processing time of a batch is equal to the largest processing time among all jobs in the batch. This problem is motivated by burn-in operations in the final testing stage of semiconductor manufacturing and is expected to occur in other production environments. We provide an exact solution procedure for the single-machine problem and heuristic algorithms for both single and parallel machine problems. While the exact algorithms have limited applicability due to high computational requirements, extensive experiments show that the heuristics are capable of consistently obtaining near-optimal solutions in very reasonable CPU times.

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This paper presents the programming an FPGA (Field Programmable Gate Array) to emulate the dynamics of DC machines. FPGA allows high speed real time simulation with high precision. The described design includes block diagram representation of DC machine, which contain all arithmetic and logical operations. The real time simulation of the machine in FPGA is controlled by user interfaces they are Keypad interface, LCD display on-line and digital to analog converter. This approach provides emulation of electrical machine by changing the parameters. Separately Exited DC machine implemented and experimental results are presented.

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This paper presents real-time simulation models of electrical machines on FPGA platform. Implementation of the real-time numerical integration methods with digital logic elements is discussed. Several numerical integrations are presented. A real-time simulation of DC machine is carried out on this FPGA platform and important transient results are presented. These results are compared to simulation results obtained through a commercial off-line simulation software.

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A geometrical structure called the implied minterm structure (IMS) has been developed from the properties of minterms of a threshold function. The IMS is useful for the manual testing of linear separability of switching functions of up to six variables. This testing is done just by inspection of the plot of the function on the IMS.

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The two-dimensional,q-state (q>4) Potts model is used as a testing ground for approximate theories of first-order phase transitions. In particular, the predictions of a theory analogous to the Ramakrishnan-Yussouff theory of freezing are compared with those of ordinary mean-field (Curie-Wiess) theory. It is found that the Curie-Weiss theory is a better approximation than the Ramakrishnan-Yussouff theory, even though the former neglects all fluctuations. It is shown that the Ramakrishnan-Yussouff theory overestimates the effects of fluctuations in this system. The reasons behind the failure of the Ramakrishnan-Yussouff approximation and the suitability of using the two-dimensional Potts model as a testing ground for these theories are discussed.

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Length scale-down (LS) model tests have been traditionally employed for laboratory studies on aeolian vibration of transmission line conductors. The span adopted is normally 30 m and is recommended by the relevant Indian, as well as other, standards. The traditionally adopted length of the LS model is reexamined herein to establish the rationale behind the choice. Based on the theoretical studies discussed, certain guidelines for the choice of model span of conductor are emphasized. In addition, the adequacy of the LS span as a tool for predicting the performance of the full span is reestablished.

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The paper presents, in three parts, a new approach to improve the detection and tracking performance of a track-while-scan radar. Part 1 presents a review of the current status of the subject. Part 2 details the new approach. It shows how a priori information provided by the tracker can be used to improve detection. It also presents a new multitarget tracking algorithm. In the present Part, analytical derivations are presented for assessing, a priori, the performance of the TWS radar system. True track initiation, false track initiation, true track continuation and false track deletion characteristics have been studied. It indicates how the various thresholds can be chosen by the designer to optimise performance. Simulation results are also presented.

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In this paper, a new approach to enhance the transmission system distance relay co-ordination is presented. The approach depends on the apparent impedance loci seen by the distance relay during all possible disturbances. In a distance relay, the impedance loci seen at the relay location is obtained by extensive transient stability studies. Support vector machines (SVMs), a class of patterns classifiers are used in discriminating zone settings (zone-1, zone-2 and zone-3) using the signals to be used by the relay. Studies on a sample 9-bus are presented for illustrating the proposed scheme.

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This paper presents a general hardware scheme for testing protective relays using microprocessor based systems. The microprocessor simulates the relaying signals for test purpose and monitors the relay performance. Based on the proposed hardware, a teat procedure for directional overcurrent relays is presented in detail. Typical test results of various routine tests conducted on a commercial single phase directional over-current relay clearly demonstrate the efficacy of the proposed technique for conducting tests on commercial relays.

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A waverider is a lifting body configuration whose upper surface is parallel to the free stream, and the lower surface aerodynamically so designed, that the resulting shock at the design Mach number, is always attached with the leading edge of the vehicle. This prevents spillage from high pressure (lower) surface to the low pressure (upper) surface.In the present study a conical waverider has been designed, fabricated and tested at Mach 6 in the IISc hypersonic shock tunnel HST2. The measurements show that the waverider has a lift to drag ratio of 4.28 at the designed Mach number. Exhaustive FEM and CFD studies are also carried out to complement the force measurements in the tunnel.

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A simple yet efficient method for the minimization of incompletely specified sequential machines (ISSMs) is proposed. Precise theorems are developed, as a consequence of which several compatibles can be deleted from consideration at the very first stage in the search for a minimal closed cover. Thus, the computational work is significantly reduced. Initial cardinality of the minimal closed cover is further reduced by a consideration of the maximal compatibles (MC's) only; as a result the method converges to the solution faster than the existing procedures. "Rank" of a compatible is defined. It is shown that ordering the compatibles, in accordance with their rank, reduces the number of comparisons to be made in the search for exclusion of compatibles. The new method is simple, systematic, and programmable. It does not involve any heuristics or intuitive procedures. For small- and medium-sized machines, it canle used for hand computation as well. For one of the illustrative examples used in this paper, 30 out of 40 compatibles can be ignored in accordance with the proposed rules and the remaining 10 compatibles only need be considered for obtaining a minimal solution.

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A simple procedure for the state minimization of an incompletely specified sequential machine whose number of internal states is not very large is presented. It introduces the concept of a compatibility graph from which the set of maximal compatibles of the machine can be very conveniently derived. Primary and secondary implication trees associated with each maximal compatible are then constructed. The minimal state machine covering the incompletely specified machine is then obtained from these implication trees.

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The room temperature (RT) tensile behaviour of a free-standing high activity Pt-aluminide bond coat has been evaluated by microtensile testing technique. The coating had a typical three-layer microstructure. The stress-strain plot for the free-standing coating was linear, indicating the coating to be brittle at RT. Different fracture features were observed across the coating layers, namely quasi-cleavage in the outer layer and inner interdiffusion zone, and cleavage in the intermediate layer. By employing interrupted tensile test and observing the cross-sectional microstructure of the tested specimens, it was determined that failure of the microtensile samples occurred by the initiation of a single crack in the intermediate layer of the coating and its subsequent inside-out propagation. Such a mechanism of failure has been explained in terms of the fracture features observed across the sample thickness. This mechanism of failure is consistent with fracture toughness values of the individual coating layers. (C) 2009 Elsevier B.V. All rights reserved.