Enhanced electrochemical performance of graphene nanosheet thin film anode decorated with tin nanoparticles

Graphene nanosheet (GNS) was synthesized by using microwave plasma enhanced CVD on copper substrate and followed by evaporation of tin metal. Scanning and transmission electron microscopy show that nanosize Sn particles are well embedded into the GNS matrix. The composition, structure, and electrochemical properties were characterized by X-ray photoelectron spectroscopy (XPS), X-ray diffraction (XRD), cyclic voltammetry (CV) and chrono-potentiometry. The first discharge capacity of as-deposited and annealed SnGNS obtained was 1551 mA h/g and 975 mA h/g, respectively. The anodes show excellent cyclic performance and coulombic efficiency.

Studies on pyridinium hexafluorostannate and its derivatives

Pyridinium hexafluorostannate, (C5H5NH)2SnF6, has been prepared by the reaction of stannous chloride or tin metal with pyridinium poly(hydrogen fluoride), PPHF, and identified by chemical analysis, IR and NMR (H-1, F-19, C-13). Making use of (C5H5NH)2SnF6 as a precursor, the following important hexafluorostannate salts have been synthesized in high yields at room temperature by ionic exchange: M2SnF6 (M = NH4, Na, K, Rb, Cs) and BaSnF6. These salts have been characterised by chemical analysis and infrared spectroscopy. Indexed powder X-ray diffraction data for Na2SnF6, Rb2SnF6 and Cs2SnF6 have been reported.

Suspended core-shell Pt-PtOx nanostructure for ultrasensitive hydrogen gas sensor

High sensitivity gas sensors are typically realized using metal catalysts and nanostructured materials, utilizing non-conventional synthesis and processing techniques, incompatible with on-chip integration of sensor arrays. In this work, we report a new device architecture, suspended core-shell Pt-PtOx nanostructure that is fully CMOS-compatible. The device consists of a metal gate core, embedded within a partially suspended semiconductor shell with source and drain contacts in the anchored region. The reduced work function in suspended region, coupled with builtin electric field of metal-semiconductor junction, enables the modulation of drain current, due to room temperature Redox reactions on exposure to gas. The device architecture is validated using Pt-PtO2 suspended nanostructure for sensing H-2 down to 200 ppb under room temperature. By exploiting catalytic activity of PtO2, in conjunction with its p-type semiconducting behavior, we demonstrate about two orders of magnitude improvement in sensitivity and limit of detection, compared to the sensors reported in recent literature. Pt thin film, deposited on SiO2, is lithographically patterned and converted into suspended Pt-PtO2 sensor, in a single step isotropic SiO2 etching. An optimum design space for the sensor is elucidated with the initial Pt film thickness ranging between 10 nm and 30 nm, for low power (< 5 mu W), room temperature operation. (C) 2015 AIP Publishing LLC.

Effect of gate-drain/source overlap on the noise in 90 nm N-channel metal oxide semiconductor field effect transistors

In this paper, we have studied the effect of gate-drain/source overlap (LOV) on the drain channel noise and induced gate current noise (SIg) in 90 nm N-channel metal oxide semiconductor field effect transistors using process and device simulations. As the change in overlap affects the gate tunneling leakage current, its effect on shot noise component of SIg has been taken into consideration. It has been shown that “control over LOV” allows us to get better noise performance from the device, i.e., it allows us to reduce noise figure, for a given leakage current constraint. LOV in the range of 0–10 nm is recommended for the 90 nm gate length transistors, in order to get the best performance in radio frequency applications.

Threshold voltage modeling under size quantization for ultra-thin silicon double-gate metal-oxide-semiconductor field-effect transistor

We report on the threshold voltage modeling of ultra-thin (1 nm-5 nm) silicon body double-gate (DG) MOSFETs using self-consistent Poisson-Schrodinger solver (SCHRED). We define the threshold voltage (V th) of symmetric DG MOSFETs as the gate voltage at which the center potential (Φ c) saturates to Φ c (s a t), and analyze the effects of oxide thickness (t ox) and substrate doping (N A) variations on V th. The validity of this definition is demonstrated by comparing the results with the charge transition (from weak to strong inversion) based model using SCHRED simulations. In addition, it is also shown that the proposed V t h definition, electrically corresponds to a condition where the inversion layer capacitance (C i n v) is equal to the oxide capacitance (C o x) across a wide-range of substrate doping densities. A capacitance based analytical model based on the criteria C i n v C o x is proposed to compute Φ c (s a t), while accounting for band-gap widening. This is validated through comparisons with the Poisson-Schrodinger solution. Further, we show that at the threshold voltage condition, the electron distribution (n(x)) along the depth (x) of the silicon film makes a transition from a strong single peak at the center of the silicon film to the onset of a symmetric double-peak away from the center of the silicon film. © 2012 American Institute of Physics.

Performance limits of transition metal dichalcogenide (MX2) nanotube surround gate ballistic field effect transistors

We theoretically analyze the performance of transition metal dichalcogenide (MX2) single wall nanotube (SWNT) surround gate MOSFET, in the 10 nm technology node. We consider semiconducting armchair (n, n) SWNT of MoS2, MoSe2, WS2, and WSe2 for our study. The material properties of the nanotubes are evaluated from the density functional theory, and the ballistic device characteristics are obtained by self-consistently solving the Poisson-Schrodinger equation under the non-equilibrium Green's function formalism. Simulated ON currents are in the range of 61-76 mu A for 4.5 nm diameter MX2 tubes, with peak transconductance similar to 175-218 mu S and ON/OFF ratio similar to 0.6 x 10(5)-0.8 x 10(5). The subthreshold slope is similar to 62.22 mV/decade and a nominal drain induced barrier lowering of similar to 12-15 mV/V is observed for the devices. The tungsten dichalcogenide nanotubes offer superior device output characteristics compared to the molybdenum dichalcogenide nanotubes, with WSe2 showing the best performance. Studying SWNT diameters of 2.5-5 nm, it is found that increase in diameter provides smaller carrier effective mass and 4%-6% higher ON currents. Using mean free path calculation to project the quasi-ballistic currents, 62%-75% reduction from ballistic values in drain current in long channel lengths of 100, 200 nm is observed.

Analysis of size quantization and temperature effects on the threshold voltage of thin silicon film double-gate metal-oxide-semiconductor field-effect transistor (MOSFET)

In this paper, we analyze the combined effects of size quantization and device temperature variations (T = 50K to 400 K) on the intrinsic carrier concentration (n(i)), electron concentration (n) and thereby on the threshold voltage (V-th) for thin silicon film (t(si) = 1 nm to 10 nm) based fully-depleted Double-Gate Silicon-on-Insulator MOSFETs. The threshold voltage (V-th) is defined as the gate voltage (V-g) at which the potential at the center of the channel (Phi(c)) begins to saturate (Phi(c) = Phi(c(sat))). It is shown that in the strong quantum confinement regime (t(si) <= 3nm), the effects of size quantization far over-ride the effects of temperature variations on the total change in band-gap (Delta E-g(eff)), intrinsic carrier concentration (n(i)), electron concentration (n), Phi(c(sat)) and the threshold voltage (V-th). On the other hand, for t(si) >= 4 nm, it is shown that size quantization effects recede with increasing t(si), while the effects of temperature variations become increasingly significant. Through detailed analysis, a physical model for the threshold voltage is presented both for the undoped and doped cases valid over a wide-range of device temperatures, silicon film thicknesses and substrate doping densities. Both in the undoped and doped cases, it is shown that the threshold voltage strongly depends on the channel charge density and that it is independent of incomplete ionization effects, at lower device temperatures. The results are compared with the published work available in literature, and it is shown that the present approach incorporates quantization and temperature effects over the entire temperature range. We also present an analytical model for V-th as a function of device temperature (T). (C) 2013 AIP Publishing LLC.

In-situ Stabilization of Tin Nanoparticles in Porous Carbon Matrix derived from Metal Organic Framework: High Capacity and High Rate Capability Anodes for Lithium-ion Batteries

It is a formidable challenge to arrange tin nanoparticles in a porous matrix for the achievement of high specific capacity and current rate capability anode for lithium-ion batteries. This article discusses a simple and novel synthesis of arranging tin nanoparticles with carbon in a porous configuration for application as anode in lithium-ion batteries. Direct carbonization of synthesized three-dimensional Sn-based MOF: K2Sn2(1,4-bdc)(3)](H2O) (1) (bdc = benzenedicarboxylate) resulted in stabilization of tin nanoparticles in a porous carbon matrix (abbreviated as Sn@C). Sn@C exhibited remarkably high electrochemical lithium stability (tested over 100 charge and discharge cycles) and high specific capacities over a wide range of operating currents (0.2-5 Ag-1). The novel synthesis strategy to obtain Sn@C from a single precursor as discussed herein provides an optimal combination of particle size and dispersion for buffering severe volume changes due to Li-Sn alloying reaction and provides fast pathways for lithium and electron transport.

Surface oxidation of cadmium, indium, tin and antimony by photoelectron and Auger spectroscopy

Surface oxidation of Cd, In, Sn and Sb has been investigated by employing valence bands, metal 4d levels and plasmon bands in X-ray photoelectron spectra. O(KLL), metal M4N45N45, and plasmon transitions in electron-induced Auger spectra as well as Auger transitions due to the metal (metal oxide) and plasmons in X-ray-induced Auger spectra. The surface oxides are In2O4, CdO and a mixture of SnO and SnO2 in the case of In. Cd and Sn respectively. The facility of surface oxidation is found to vary as In>Cd>Sn>Sb. Inter-atomic Auger transitions involving oxygen valence bands have been identified on oxidized surfaces of Cd and In.

A study of the nature of coordination in metal monothiocarbamates based on infrared spectroscopy and the HSAB concept

The nature of coordination in metal monothiocarbamates is shown to depend on the hardness or softness of the metal ton. Thus, the monothiocarbamate ion acts as a monodentate ligand with metal-sulphur bending when the metal ion is a soft acid while it acts as a bidentate ligand when the metal ion is a hard acid; it can exhibit either behaviour when the metal ion is a borderline acid. In dialkyltin and dialkylmonocholorotin complexes, the monothiocarbamate ion acts as a bidentate ligand with strong Sn-S bonding while in trialkyl-or triaryl-tin complexes it acts essentially as a monodentate ligand. Thus, R3Sn(I) seems to be a soft or borderline acid while R2Sn(II) is a hard acid.

Analytical modeling of quantum threshold voltage for triple gate MOSFET

In this work a physically based analytical quantum threshold voltage model for the triple gate long channel metal oxide semiconductor field effect transistor is developed The proposed model is based on the analytical solution of two-dimensional Poisson and two-dimensional Schrodinger equation Proposed model is extended for short channel devices by including semi-empirical correction The impact of effective mass variation with film thicknesses is also discussed using the proposed model All models are fully validated against the professional numerical device simulator for a wide range of device geometries (C) 2010 Elsevier Ltd All rights reserved

The Archaeometallurgical Implications of New Findings of Traditional Crafts of Making High Tin ‘Delta’ Bronze Mirrors and ‘Beta’ Bronze Vessels in Kerala State of South India

New metallurgical and ethnographic observations of the traditional manufacture of specular high-tin bronze mirrors in Kerala state of southern India are discussed, which is an exceptional example of a surviving craft practice of metal mirror-making in the world. The manufacturing process has been reconstructed from analytical investigations made by Srinivasan following a visit late in 1991 to a mirror making workshop and from her technical studies of equipment acquired by Glover in March 1992 from another group of mirror makers from Pathanamthita at an exhibition held at Crafts Museum, Delhi. Finished and unfinished mirror from two workshops were of a binary, copper-tin alloy of 33% tin which is close to the composition of pure delta phase, so that these mirrors are referred to here as ‘delta’ bronzes. For the first time, metallurgical and field observations were made by Srinivasan in 1991 of the manufacture of high-tin ‘beta’ bonze vessels from Palghat district, Kerala, i‥e of wrought and quenched 23% tin bronze. This has provided the first metallurgical record for a surviving craft of high-tin bronze bowl making which can be directly related to archaeological finds of high-tin bronze vessels from the Indian subcontinent and Southeast Asia. New analytical investigations are presented of high-tin beta bronzes from the Indian subcontinent which are some of the earliest reported worldwide. These coupled with the archaeometallurgical evidence suggests that these high-tin bronze techniques are part of a long, continuing, and probably indigenous tradition of the use of high-tin bronzes in the Indian subcontinent with finds reported even from Indus Valley sites. While the source of tin has been problematic, new evidence on bronze smelting slags and literary evidence suggests there may have been some sources of tin in South India.

A Simulation Based Study and Analysis of Double Gate Tunnel FET Performance for Low Stand-By Power Applications

The conventional metal oxide semiconductor field effect transistor (MOSFET)may not be suitable for future low standby power (LSTP) applications due to its high off-state current as the sub-threshold swing is theoretically limited to 60mV/decade. Tunnel field effect transistor (TFET) based on gate controlled band to band tunneling has attracted attention for such applications due to its extremely small sub-threshold swing (much less than 60mV/decade). This paper takes a simulation approach to gain some insight into its electrostatics and the carrier transport mechanism. Using 2D device simulations, a thorough study and analysis of the electrical parameters of the planar double gate TFET is performed. Due to excellent sub-threshold characteristics and a reverse biased structure, it offers orders of magnitude less leakage current compared to the conventional MOSFET. In this work, it is shown that the device can be scaled down to channel lengths as small as 30 nm without affecting its performance. Also, it is observed that the bulk region of the device plays a major role in determining the sub-threshold characteristics of the device and considerable improvement in performance (in terms of ION/IOFF ratio) can be achieved if the thickness of the device is reduced. An ION/IOFF ratio of 2x1012 and a minimum point sub-threshold swing of 22mV/decade is obtained.

A Simple Charge Model for Symmetric Double-Gate MOSFETs Adapted to Gate-Oxide-Thickness Asymmetry

Surface-potential-based compact charge models for symmetric double-gate metal-oxide-semiconductor field-effect transistors (SDG-MOSFETs) are based on the fundamental assumption of having equal oxide thicknesses for both gates. However, for practical devices, there will always be some amount of asymmetry between the gate oxide thicknesses due to process variations and uncertainties, which can affect device performance significantly. In this paper, we propose a simple surface-potential-based charge model, which is applicable for tied double-gate MOSFETs having same gate work function but could have any difference in gate oxide thickness. The proposed model utilizes the unique so-far-unexplored quasi-linear relationship between the surface potentials along the channel. In this model, the terminal charges could be computed by basic arithmetic operations from the surface potentials and applied biases, and thus, it could be implemented in any circuit simulator very easily and extendable to short-channel devices. We also propose a simple physics-based perturbation technique by which the surface potentials of an asymmetric device could be obtained just by solving the input voltage equation of SDG devices for small asymmetry cases. The proposed model, which shows excellent agreement with numerical and TCAD simulations, is implemented in a professional circuit simulator through the Verilog-A interface and demonstrated for a 101-stage ring oscillator simulation. It is also shown that the proposed model preserves the source/drain symmetry, which is essential for RF circuit design.

Influence of sputter power on structural and electrical properties of TiO2 films for Al/TiO2/Si gate capacitors

Titanium dioxide (TiO2) thin films were deposited onto p-Si substrates held at room temperature by reactive Direct Current (DC) magnetron sputtering at various sputter powers in the range 80-200W. The as-deposited TiO2 films were annealed at a temperature of 1023K. The post-annealed films were characterized for crystallographic structure, chemical binding configuration, surface morphology and optical absorption. The electrical and dielectric properties of Al/TiO2/p-Si structure were determined from the capacitance-voltage and current-voltage characteristics. X-ray diffraction studies confirmed that the as-deposited films were amorphous in nature. After post-annealing at 1023K, the films formed at lower powers exhibited anatase phase, where as those deposited at sputter powers >160W showed the mixed anatase and rutile phases of TiO2. The surface morphology of the films varied significantly with the increase of sputter power. The electrical and dielectric properties on the air-annealed Al/TiO2/p-Si structures were studied. The effect of sputter power on the electrical and dielectric characteristics of the structure of Al/TiO2/p-Si (metal-insulator-semiconductor) was systematically investigated. Copyright (c) 2014 John Wiley & Sons, Ltd.