9 resultados para Solder and soldering

em Indian Institute of Science - Bangalore - Índia


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The effect of different pre-aging treatments on the microstructural evolution of lead-free solder and growth of interfacial intermetallic compound layers under thermal cycling has been investigated in this work. The results show that there are distinct differences in the microstructural changes between samples with no pretreatment, samples that have experienced thermal annealing at 125A degrees C for 750 h before thermal cycling, and those that have had direct current (DC) stressing for 750 h as pretreatment. The microstructural evolution of the solder matrix is rationalized by utilizing the science of microstructures and analysis of the influence of electron flow on the precipitation phenomena. The finite-element method is utilized to understand the loading conditions imposed on the solder interconnections during cyclic stressing. The growth of intermetallic reaction layers is further analyzed by utilizing quantitative thermodynamic calculations coupled with kinetic analysis. The latter is based on the changes in the intrinsic diffusion fluxes of elements induced by current flow and alloying elements present in the system. With this concurrent approach the differences seen in thermal cycling behavior between the different pre-aging treatments can be explained.

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Othman et al. (Intermetallics 2012;22:1-6) recently published a manuscript on ``Effects of current density on the formation and microstructure of Sn-9Zn, Sn-8Zn-3Bi and Sn-3Ag-0.5Cu solder joints''. We found problems in calculation of diffusion parameters. Even the comment on the formation of Cu5Zn8 instead of Cu6Sn5 is not correct. In this comment, we have explained the correct procedure to calculate the diffusion coefficients. Further, we have also explained the reason for the formation of Cu5Zn8 instead of Cu6Sn5 in the Cu/Sn-9Zn system. (C) 2012 Elsevier Ltd. All rights reserved.

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Sn-Ag-Cu (SAC) solders are susceptible to appreciable microstructural coarsening during storage or service. This results in evolution of joint properties over time and thereby influences the long-term reliability of microelectronic packages. Accurate reliability prediction of SAC solders requires prediction of microstructural evolution during service. Microstructure evolution in two SAC solder alloys, such as, Sn-3.0Ag-0.5Cu (SAC 305) and Sn-1.0Ag-0.5 Cu (SAC 105), under different thermomechanical excursions, including isothermal aging at 150 degrees C and thermomechanical cycling (TMC) was studied. In general, between 200 and 600 cycles during TMC, recrystallization of the Sn matrix was observed, along with redistribution of Ag3Sn particles because of dissolution and reprecipitation. These latter effects have not been reported before. It was also observed that the Sn grains recrystallized near precipitate clusters in eutectic channels during extended isothermal aging. The relative orientation of Sn grains in proeutectic colonies did not change during isothermal aging.

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Solder joints in electronic packages undergo thermo-mechanical cycling, resulting in nucleation of micro-cracks, especially at the solder/bond-pad interface, which may lead to fracture of the joints. The fracture toughness of a solder joint depends on material properties, process conditions and service history, as well as strain rate and mode-mixity. This paper reports on a methodology for determining the mixed-mode fracture toughness of solder joints with an interfacial starter-crack, using a modified compact mixed mode (CMM) specimen containing an adhesive joint. Expressions for stress intensity factor (K) and strain energy release rate (G) are developed, using a combination of experiments and finite element (FE) analysis. In this methodology, crack length dependent geometry factors to convert for the modified CMM sample are first obtained via the crack-tip opening displacement (CTOD)-based linear extrapolation method to calculate the under far-field mode I and II conditions (f(1a) and f(2a)), (ii) generation of a master-plot to determine a(c), and (iii) computation of K and G to analyze the fracture behavior of joints. The developed methodology was verified using J-integral calculations, and was also used to calculate experimental fracture toughness values of a few lead-free solder-Cu joints. (C) 2014 Elsevier Ltd. All rights reserved.

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One of the foremost design considerations in microelectronics miniaturization is the use of embedded passives which provide practical solution. In a typical circuit, over 80 percent of the electronic components are passives such as resistors, inductors, and capacitors that could take up to almost 50 percent of the entire printed circuit board area. By integrating passive components within the substrate instead of being on the surface, embedded passives reduce the system real estate, eliminate the need for discrete and assembly, enhance electrical performance and reliability, and potentially reduce the overall cost. Moreover, it is lead free. Even with these advantages, embedded passive technology is at a relatively immature stage and more characterization and optimization are needed for practical applications leading to its commercialization.This paper presents an entire process from design and fabrication to electrical characterization and reliability test of embedded passives on multilayered microvia organic substrate. Two test vehicles focusing on resistors and capacitors have been designed and fabricated. Embedded capacitors in this study are made with polymer/ceramic nanocomposite (BaTiO3) material to take advantage of low processing temperature of polymers and relatively high dielectric constant of ceramics and the values of these capacitors range from 50 pF to 1.5 nF with capacitance per area of approximately 1.5 nF/cm(2). Limited high frequency measurement of these capacitors was performed. Furthermore, reliability assessments of thermal shock and temperature humidity tests based on JEDEC standards were carried out. Resistors used in this work have been of three types: 1) carbon ink based polymer thick film (PTF), 2) resistor foils with known sheet resistivities which are laminated to printed wiring board (PWB) during a sequential build-up (SBU) process and 3) thin-film resistor plating by electroless method. Realization of embedded resistors on conventional board-level high-loss epoxy (similar to 0.015 at 1 GHz) and proposed low-loss BCB dielectric (similar to 0.0008 at > 40 GHz) has been explored in this study. Ni-P and Ni-W-P alloys were plated using conventional electroless plating, and NiCr and NiCrAlSi foils were used for the foil transfer process. For the first time, Benzocyclobutene (BCB) has been proposed as a board level dielectric for advanced System-on-Package (SOP) module primarily due to its attractive low-loss (for RF application) and thin film (for high density wiring) properties.Although embedded passives are more reliable by eliminating solder joint interconnects, they also introduce other concerns such as cracks, delamination and component instability. More layers may be needed to accommodate the embedded passives, and various materials within the substrate may cause significant thermo -mechanical stress due to coefficient of thermal expansion (CTE) mismatch. In this work, numerical models of embedded capacitors have been developed to qualitatively examine the effects of process conditions and electrical performance due to thermo-mechanical deformations.Also, a prototype working product with the board level design including features of embedded resistors and capacitors are underway. Preliminary results of these are presented.

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In this paper the effects of constant and cyclic power loads on the evolution of interfacial reaction layers in lead-free solder interconnections are presented. Firstly, the differences in the growth behavior of intermetallic compound (IMC) layers at the cathode and anode sides of the interconnections are rationalized. This is done by considering the changes in the intrinsic fluxes of elements owing to electromigration as well as taking into account the fact that the growth of Cu3Sn and Cu6Sn5 are coupled via interfacial reactions. In this way, better understanding of the effect of electron flux on the growth of each individual layer in the Cu-Sn system can be achieved. Secondly, it is shown that there is a distinct difference between steady-state current stressing (constant current, constant temperature) and power cycling with alternating on- and off-cycle periods (accompanied by a change of temperature). The reasons behind the observed differences are subsequently discussed. Finally, special care is taken to ensure that the current densities are chosen in such a way that there is no risk for even partial melting of the solder interconnections.

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Sn-Ag-Cu (SAC) solders are susceptible to appreciable microstructural coarsening during storage or service. This results in evolution of joint properties over time, and thereby influences the long-term reliability of microelectronic packages. Accurate prediction of this aging behavior is therefore critical for joint reliability predictions. Here, we study the precipitate coarsening behavior in two Sn-Ag-Cu (SAC) alloys, namely Sn-3.0Ag-0.5Cu and Sn-1.0Cu-0.5Cu, under different thermo-mechanical excursions, including isothermal aging at 150 degrees C for various lengths of time and thermo-mechanical cycling between -25 degrees C and 125 degrees C, with an imposed shear strain of similar to 19.6% per cycle, for different number of cycles. During isothermal aging and the thermo-mechanical cycling up to 200 cycles, Ag3Sn precipitates undergo rapid, monotonous coarsening. However, high number of thermo-mechanical cycling, usually between 200 and 600 cycles, causes dissolution and re-precipitation of precipitates, resulting in a fine and even distribution. Also, recrystallization of Sn-grains near precipitate clusters was observed during severe isothermal aging. Such responses are quite unusual for SAC solder alloys. In the regime of usual precipitate coarsening in these SAC alloys, an explicit parameter, which captures the thermo-mechanical history dependence of Ag3Sn particle size, was defined. Brief mechanistic description for the recrystallization of Sn grains during isothermal aging and reprecipitation of the Ag3Sn due to high number of thermo-mechanical cycles are also presented.

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A fracture mechanism map (FMM) is a powerful tool which correlates the fracture behavior of a material to its microstructural characteristics in an explicit and convenient way. In the FMM for solder joints, an effective thickness of the interfacial intermetallic compound (IMC) layer (t (eff)) and the solder yield strength (sigma (ys,eff)) are used as abscissa and ordinate axes, respectively, as these two predominantly affect the fracture behavior of solder joints. Earlier, a definition of t (eff), based on the uniform thickness of IMC (t (u)) and the average height of the IMC scallops (t (s)), was proposed and shown to aptly explain the fracture behavior of solder joints on Cu. This paper presents a more general definition of t (eff) that is more widely applicable to a range of metallizations, including Cu and electroless nickel immersion gold (ENIG). Using this new definition of t (eff), mode I FMM for SAC387/Cu joints has been updated and its validity was confirmed. A preliminary FMM for SAC387/Cu joints with ENIG metallization is also presented.

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When dropped, electronic packages often undergo failure by propagation of an interfacial crack in solder joints under a combination of tensile and shear loading. Hence, it is crucial to understand and predict the fracture behavior of solder joints under mixed-mode high-rate loading conditions. In this work, the effects of the loading conditions (strain rate and loading angle) and microstructure interfacial intermetallic compound (IMC) morphology and solder yield strength] on the mixed-mode fracture toughness of Sn-3.8 wt.%Ag-0.7 wt.%Cu solder joints sandwiched between two Cu substrates with electroless nickel immersion gold (ENIG) metallization have been studied, and compared with the fracture behavior of joints attached to bare Cu. Irrespective of the surface finish, the fracture toughness of the solder joints decreased monotonically with strain rate and mode-mixity, both resulting in increased fracture proportion through the interfacial IMC layer. Furthermore, the proportion of crack propagation through the interfacial IMC layer increased with increase in the thickness and the roughness of the interfacial IMC layer and the yield strength of the solder, resulting in a decrease in the fracture toughness of the joint. However, under most conditions, solder joints with ENIG finish showed higher resistance to fracture than joints attached directly to Cu substrates without ENIG metallization. Based on the experimental observations, a fracture mechanism map is constructed correlating the yield strength of the solder, the morphology and thickness of the interfacial IMC, and the fracture mechanisms as well as the fracture toughness values for different solder joints under mode I loading.