Click Chemistry Inspired Synthesis of Novel Ferrocenyl-Substituted Amino Acids or Peptides

This work reports on the synthesis of a wide range of ferrocenyl-substituted amino acids and peptides in excellent yield. Conjugation is established via copper-catalyzed 1,3-dipolar cycloaddition. Two complementary strategies were employed for conjugation, one involving cycloaddition of amino acid derived azides with ethynyl ferrocene 1 and the other involves cycloaddition between amino acid derived alkynes with ferrocene-derived azides 2 and 3. Labeling of amino acids at multiple sites with ferrocene is discussed. A new route to 1,1'-unsymmetrically substituted ferrocene conjugates is reported. A novel ferrocenophane 19 is accessed via bimolecular condensation of amino acid derived bis-alkyne 9b with the azide 2. The electrochemical behavior of some selected ferrocene conjugates has been studied by cyclic voltammetry.

Site-Specific Functionalization of Hyperbranched Polymers Using ``Click'' Chemistry

Different strategies for functionalization of the core region and periphery of core-shell type hyperbranched polymers (HBP) using the ``click'' reaction have been explored. For achieving periphera functionalization, an AB(2) + A-R-1 + A-R-2 type copolymerization approach was used, where A-R-1 is heptaethylene glycol monomethyl ether (HPEG-M) and A-R-2 is tetraethylene glycol monopropargyl ether (TEG-P). A very small mole fraction of the propargyl containing monomer, TEG-P, was used to ensure that the water-solubility of the hyperbranched polymer is minimally affected. Similarly, to incorporate propargyl groups in the core region, a new propargyl group bearing B-2-typ monomer was designed and utilized in an AB(2) + A(2) + B-2 + A-R-1 type copolymerization, such that the total mole fraction of B-2 + A(2) is small and their mole-ratio is 1: 1. Further, using a combination of both the above approaches, namely AB(2) + A(2) + B-2 + A-R-1 + A-R-2, hyperbranched structures that incorporate propargyl groups both at theperiphery and within the core were synthesized. Since the AB(2) monomer carries a hexamethylene spacer (C-6) and the periphery is PEGylated all the derivatized polymers form core-shell type structures in aqueous solutions. Attempts were made to ascertain and probe the location of the propargyl groups in these HBP's, by ``clicking'' azidomethylpyrene, onto them. However, the fluorescence spectra of aqueous solutions of the pyrene derivatized polymers were unable to discriminate between the various locations, possibly because the relatively hydrophobic pyrene units insert themselves into the core region to minimize exposure to water.

RECONNECT: A NoC for polymorphic ASICs using a low overhead single cycle router

A polymorphic ASIC is a runtime reconfigurable hardware substrate comprising compute and communication elements. It is a ldquofuture proofrdquo custom hardware solution for multiple applications and their derivatives in a domain. Interoperability between application derivatives at runtime is achieved through hardware reconfiguration. In this paper we present the design of a single cycle Network on Chip (NoC) router that is responsible for effecting runtime reconfiguration of the hardware substrate. The router design is optimized to avoid FIFO buffers at the input port and loop back at output crossbar. It provides virtual channels to emulate a non-blocking network and supports a simple X-Y relative addressing scheme to limit the control overhead to 9 bits per packet. The 8times8 honeycomb NoC (RECONNECT) implemented in 130 nm UMC CMOS standard cell library operates at 500 MHz and has a bisection bandwidth of 28.5 GBps. The network is characterized for random, self-similar and application specific traffic patterns that model the execution of multimedia and DSP kernels with varying network loads and virtual channels. Our implementation with 4 virtual channels has an average network latency of 24 clock cycles and throughput of 62.5% of the network capacity for random traffic. For application specific traffic the latency is 6 clock cycles and throughput is 87% of the network capacity.

Discovering user preferences by using time entries in click-through data to improve search engine results

The search engine log files have been used to gather direct user feedback on the relevancy of the documents presented in the results page. Typically the relative position of the clicks gathered from the log files is used a proxy for the direct user feedback. In this paper we identify reasons for the incompleteness of the relative position of clicks for deciphering the user preferences. Hence, we propose the use of time spent by the user in reading through the document as indicative of user preference for a document with respect to a query. Also, we identify the issues involved in using the time measure and propose means to address them.

Click chemistry inspired synthesis of ferrocene amino acids and other derivatives

This work reports the synthesis of a wide range of ferrocenyl-amino acids and other derivatives in excellent yield. Diverse amino acid containing azides were synthesized and ligated to ferrocene employing click reaction to access ferrocenyl amino acids. Chiral alcohols, esters, diols, amines containing azido group were tagged to ferrocene via click reaction to generate ferrocene derived chiral derivatives. A novel strategy for direct incorporation of ferrocene into a peptide and a new route to 1, 1′disubstituted ferrocene amino acid derivative are reported.

Vesicle and Stable Monolayer Formation from Simple ``Click'' Chemistry Adducts in Water

Click chemistry has been successfully extended into the field of molecular design of novel amphiphatic adducts. After their syntheses and characterizations, we have studied their aggregation properties in aqueous medium. Each of these adducts forms stable suspensions in water. These suspensions have been characterized by dynamic light scattering (DLS) studies and transmission electron microscopy (TEM). The presence of inner aqueous compartments in such aggregates has been demonstrated using dye (methylene blue) entrapment studies. These aggregates have been further characterized using X-ray diffraction (XRD), which indicates the existence of bilayer structures in them. Therefore, the resulting aggregates could be described as vesicles. The temperature-induced order-to-disorder transitions of the vesicular aggregates and the accompanying changes in their packing and hydration have been examined using high-sensitivity differential scanning calorimetry, fluorescence anisotropy, and generalized polarization measurements using appropriate membrane-soluble probe, 1,6-diphenylhexatriene, and Paldan, respectively. The findings of these studies are consistent with each other in terms of the apparent phase transition temperatures. Langmuir monolayer studies confirmed that these click adducts also form stable monolayers on buffered aqueous subphase at the air-water interface.

10 Years of Click Chemistry: Synthesis and Applications of Ferrocene-Derived Triazoles

Click chemistry has played a significant role as a rapid and versatile strategy for conjugating two molecular fragments under very mild reaction conditions. Introduction of ferrocene-derived triazole systems using click chemistry has attracted enormous interest in various fields due to its potential applications in electrochemical techniques for detection and sensing. The present discussion focuses on the synthesis of ferrocene-triazole and the importance of using a CuAAC reaction for such conjugation. Applications of ferrocene-based click reactions in conjugate chemistry, asymmetric catalysis, medicinal chemistry, host-guest interactions, and materials chemistry have been highlighted.

Glycidyl azide polymer crosslinked through triazoles by click chemistry: curing, mechanical and thermal properties

Glycidyl azide polymer (GAP) was cured through click chemistry by reaction of the azide group with bispropargyl succinate (BPS) through a 1,3-dipolar cycloaddition reaction to form 1,2,3-triazole network. The properties of GAP-based triazole networks are compared with the urethane cured GAP-systems. The glass transition temperature (T-g), tensile strength, and modulus of the system increased with crosslink density, controlled by the azide to propargyl ratio. The triazole incorporation has a higher T-g in comparison to the GAP-urethane system (T-g-20 degrees C) and the networks exhibit biphasic transitions at 61 and 88 degrees C. The triazole curing was studied using Differential Scanning Calorimetry (DSC) and the related kinetic parameters were helpful for predicting the cure profile at a given temperature. Density functional theory (DFT)-based theoretical calculations implied marginal preference for 1,5-addition over 1,4-addition for the cycloaddition between azide and propargyl group. Thermogravimetic analysis (TG) showed better thermal stability for the GAP-triazole and the mechanism of decomposition was elucidated using pyrolysis GC-MS studies. The higher heat of exothermic decomposition of triazole adduct (418kJmol(-1)) against that of azide (317kJmol(-1)) and better mechanical properties of the GAP-triazole renders it a better propellant binder than the GAP-urethane system.

An Implementation of Partitioned Scheduling Scheme for Hard Real-Time Tasks in Multicore Linux with Fair Share for Linux Tasks

The correctness of a hard real-time system depends its ability to meet all its deadlines. Existing real-time systems use either a pure real-time scheduler or a real-time scheduler embedded as a real-time scheduling class in the scheduler of an operating system (OS). Existing implementations of schedulers in multicore systems that support real-time and non-real-time tasks, permit the execution of non-real-time tasks in all the cores with priorities lower than those of real-time tasks, but interrupts and softirqs associated with these non-real-time tasks can execute in any core with priorities higher than those of real-time tasks. As a result, the execution overhead of real-time tasks is quite large in these systems, which, in turn, affects their runtime. In order that the hard real-time tasks can be executed in such systems with minimal interference from other Linux tasks, we propose, in this paper, an integrated scheduler architecture, called SchedISA, which aims to considerably reduce the execution overhead of real-time tasks in these systems. In order to test the efficacy of the proposed scheduler, we implemented partitioned earliest deadline first (P-EDF) scheduling algorithm in SchedISA on Linux kernel, version 3.8, and conducted experiments on Intel core i7 processor with eight logical cores. We compared the execution overhead of real-time tasks in the above implementation of SchedISA with that in SCHED_DEADLINE's P-EDF implementation, which concurrently executes real-time and non-real-time tasks in Linux OS in all the cores. The experimental results show that the execution overhead of real-time tasks in the above implementation of SchedISA is considerably less than that in SCHED_DEADLINE. We believe that, with further refinement of SchedISA, the execution overhead of real-time tasks in SchedISA can be reduced to a predictable maximum, making it suitable for scheduling hard real-time tasks without affecting the CPU share of Linux tasks.

Dendron conjugation to graphene oxide using click chemistry for efficient gene delivery

Owing to its large surface area and rapid cellular uptake, graphene oxide (GO) is emerging as an attractive candidate material for delivery of drugs and genes. The inherent sp(2) pi-pi interaction of GO helps to carry drugs and single stranded RNA (ssRNA) but there is no such interaction with double stranded DNA (dsDNA). In this work, a polyamidoamine (PAMAM) dendron was conjugated with nano GO (nGO) through ``click'' chemistry to improve the DNA complexation capability of GO as well as its transfection efficiency. The DNA complexation capability of GO was significantly enhanced after dendronization of GO yielding spherical nanosized (250-350 nm) particles of the dendronized GO (DGO)/pDNA complex with a positive zeta potential. The transfection efficiency of GO dramatically increased after conjugation of the PAMAM dendron. Transfection efficiency of 51% in HeLa cells with cell viability of 80% was observed. The transfection efficiency was significantly higher than that of polyethyleneimine 25 kDa (27% efficiency) and also surpassed that of lipofectamine 2000 (47% efficiency). The uptake of the DGO/pDNA complex by the caveolae mediated endocytosis pathway may significantly contribute to the high transfection efficiency. Thus, dendronized GO is shown to be an efficient gene carrier with minimal toxicity and is a promising candidate for use as a nonviral carrier for gene therapy.

Router Attack toward NoC-enabled MPSoC and Monitoring Countermeasures against such Threat

The growing number of applications and processing units in modern Multiprocessor Systems-on-Chips (MPSoCs) come along with reduced time to market. Different IP cores can come from different vendors, and their trust levels are also different, but typically they use Network-on-Chip (NoC) as their communication infrastructure. An MPSoC can have multiple Trusted Execution Environments (TEEs). Apart from performance, power, and area research in the field of MPSoC, robust and secure system design is also gaining importance in the research community. To build a secure system, the designer must know beforehand all kinds of attack possibilities for the respective system (MPSoC). In this paper we survey the possible attack scenarios on present-day MPSoCs and investigate a new attack scenario, i.e., router attack targeted toward NoC architecture. We show the validity of this attack by analyzing different present-day NoC architectures and show that they are all vulnerable to this type of attack. By launching a router attack, an attacker can control the whole chip very easily, which makes it a very serious issue. Both routing tables and routing logic-based routers are vulnerable to such attacks. In this paper, we address attacks on routing tables. We propose different monitoring-based countermeasures against routing table-based router attack in an MPSoC having multiple TEEs. Synthesis results show that proposed countermeasures, viz. Runtime-monitor, Restart-monitor, Intermediate manager, and Auditor, occupy areas that are 26.6, 22, 0.2, and 12.2 % of a routing table-based router area. Apart from these, we propose Ejection address checker and Local monitoring module inside a router that cause 3.4 and 10.6 % increase of a router area, respectively. Simulation results are also given, which shows effectiveness of proposed monitoring-based countermeasures.

Query Click and Text Similarity Graph for Query Suggestions

Query suggestion is an important feature of the search engine with the explosive and diverse growth of web contents. Different kind of suggestions like query, image, movies, music and book etc. are used every day. Various types of data sources are used for the suggestions. If we model the data into various kinds of graphs then we can build a general method for any suggestions. In this paper, we have proposed a general method for query suggestion by combining two graphs: (1) query click graph which captures the relationship between queries frequently clicked on common URLs and (2) query text similarity graph which finds the similarity between two queries using Jaccard similarity. The proposed method provides literally as well as semantically relevant queries for users' need. Simulation results show that the proposed algorithm outperforms heat diffusion method by providing more number of relevant queries. It can be used for recommendation tasks like query, image, and product suggestion.

A Scalable High Throughput Firewall in FPGA

High end network security applications demand high speed operation and large rule set support. Packet classification is the core functionality that demands high throughput in such applications. This paper proposes a packet classification architecture to meet such high throughput. We have implemented a Firewall with this architecture in reconflgurable hardware. We propose an extension to Distributed Crossproducting of Field Labels (DCFL) technique to achieve scalable and high performance architecture. The implemented Firewall takes advantage of inherent structure and redundancy of rule set by using our DCFL Extended (DCFLE) algorithm. The use of DCFLE algorithm results in both speed and area improvement when it is implemented in hardware. Although we restrict ourselves to standard 5-tuple matching, the architecture supports additional fields. High throughput classification invariably uses Ternary Content Addressable Memory (TCAM) for prefix matching, though TCAM fares poorly in terms of area and power efficiency. Use of TCAM for port range matching is expensive, as the range to prefix conversion results in large number of prefixes leading to storage inefficiency. Extended TCAM (ETCAM) is fast and the most storage efficient solution for range matching. We present for the first time a reconfigurable hardware implementation of ETCAM. We have implemented our Firewall as an embedded system on Virtex-II Pro FPGA based platform, running Linux with the packet classification in hardware. The Firewall was tested in real time with 1 Gbps Ethernet link and 128 sample rules. The packet classification hardware uses a quarter of logic resources and slightly over one third of memory resources of XC2VP30 FPGA. It achieves a maximum classification throughput of 50 million packet/s corresponding to 16 Gbps link rate for the worst case packet size. The Firewall rule update involves only memory re-initialization in software without any hardware change.

A do-it-yourself (DIY) switched mode power conversion laboratory

In the education of physical sciences, the role of the laboratory cannot be overemphasised. It is the laboratory exercises which enable the student to assimilate the theoretical basis, verify the same through bench-top experiments, and internalize the subject discipline to acquire mastery of the same. However the resources essential to put together such an environment is substantial. As a result, the students go through a curriculum which is wanting in this respect. This paper presents a low cost alternative to impart such an experience to the student aimed at the subject of switched mode power conversion. The resources are based on an open source circuit simulator (Sequel) developed at IIT Mumbai, and inexpensive construction kits developed at IISc Bangalore. The Sequel programme developed by IIT Mumbai, is a circuit simulation program under linux operating system distributed free of charge. The construction kits developed at IISc Bangalore, is fully documented for anyone to assemble these circuit which minimal equipment such as soldering iron, multimeter, power supply etc. This paper puts together a simple forward dc to dc converter as a vehicle to introduce the programming under sequel to evaluate the transient performance and small signal dynamic model of the same. Bench tests on the assembled construction kit may be done by the student for study of operation, transient performance and closed loop stability margins etc.

A Scalable High Throughput Firewall in FPGA

High end network security applications demand high speed operation and large rule set support. Packet classification is the core functionality that demands high throughput in such applications. This paper proposes a packet classification architecture to meet such high throughput. We have Implemented a Firewall with this architecture in reconfigurable hardware. We propose an extension to Distributed Crossproducting of Field Labels (DCFL) technique to achieve scalable and high performance architecture. The implemented Firewall takes advantage of inherent structure and redundancy of rule set by using, our DCFL Extended (DCFLE) algorithm. The use of DCFLE algorithm results In both speed and area Improvement when It is Implemented in hardware. Although we restrict ourselves to standard 5-tuple matching, the architecture supports additional fields.High throughput classification Invariably uses Ternary Content Addressable Memory (TCAM) for prefix matching, though TCAM fares poorly In terms of area and power efficiency. Use of TCAM for port range matching is expensive, as the range to prefix conversion results in large number of prefixes leading to storage inefficiency. Extended TCAM (ETCAM) is fast and the most storage efficient solution for range matching. We present for the first time a reconfigurable hardware Implementation of ETCAM. We have implemented our Firewall as an embedded system on Virtex-II Pro FPGA based platform, running Linux with the packet classification in hardware. The Firewall was tested in real time with 1 Gbps Ethernet link and 128 sample rules. The packet classification hardware uses a quarter of logic resources and slightly over one third of memory resources of XC2VP30 FPGA. It achieves a maximum classification throughput of 50 million packet/s corresponding to 16 Gbps link rate for file worst case packet size. The Firewall rule update Involves only memory re-initialiization in software without any hardware change.