Fault tolerance in multiprocessor systems

Multiprocessor systems which afford a high degree of parallelism are used in a variety of applications. The extremely stringent reliability requirement has made the provision of fault-tolerance an important aspect in the design of such systems. This paper presents a review of the various approaches towards tolerating hardware faults in multiprocessor systems. It. emphasizes the basic concepts of fault tolerant design and the various problems to be taken care of by the designer. An indepth survey of the various models, techniques and methods for fault diagnosis is given. Further, we consider the strategies for fault-tolerance in specialized multiprocessor architectures which have the ability of dynamic reconfiguration and are suited to VLSI implementation. An analysis of the state-óf-the-art is given which points out the major aspects of fault-tolerance in such architectures.

Role of information and communication in redefining unmanned aerial vehicle autonomous control levels

Autonomous mission control, unlike automatic mission control which is generally pre-programmed to execute an intended mission, is guided by the philosophy of carrying out a complete mission on its own through online sensing, information processing, and control reconfiguration. A crucial cornerstone of this philosophy is the capability of intelligence and of information sharing between unmanned aerial vehicles (UAVs) or with a central controller through secured communication links. Though several mission control algorithms, for single and multiple UAVs, have been discussed in the literature, they lack a clear definition of the various autonomous mission control levels. In the conventional system, the ground pilot issues the flight and mission control command to a UAV through a command data link and the UAV transmits intelligence information, back to the ground pilot through a communication link. Thus, the success of the mission depends entirely on the information flow through a secured communication link between ground pilot and the UAV In the past, mission success depended on the continuous interaction of ground pilot with a single UAV, while present day applications are attempting to define mission success through efficient interaction of ground pilot with multiple UAVs. However, the current trend in UAV applications is expected to lead to a futuristic scenario where mission success would depend only on interaction among UAV groups with no interaction with any ground entity. However, to reach this capability level, it is necessary to first understand the various levels of autonomy and the crucial role that information and communication plays in making these autonomy levels possible. This article presents a detailed framework of UAV autonomous mission control levels in the context of information flow and communication between UAVs and UAV groups for each level of autonomy.

RECONNECT: A NoC for polymorphic ASICs using a low overhead single cycle router

A polymorphic ASIC is a runtime reconfigurable hardware substrate comprising compute and communication elements. It is a ldquofuture proofrdquo custom hardware solution for multiple applications and their derivatives in a domain. Interoperability between application derivatives at runtime is achieved through hardware reconfiguration. In this paper we present the design of a single cycle Network on Chip (NoC) router that is responsible for effecting runtime reconfiguration of the hardware substrate. The router design is optimized to avoid FIFO buffers at the input port and loop back at output crossbar. It provides virtual channels to emulate a non-blocking network and supports a simple X-Y relative addressing scheme to limit the control overhead to 9 bits per packet. The 8times8 honeycomb NoC (RECONNECT) implemented in 130 nm UMC CMOS standard cell library operates at 500 MHz and has a bisection bandwidth of 28.5 GBps. The network is characterized for random, self-similar and application specific traffic patterns that model the execution of multimedia and DSP kernels with varying network loads and virtual channels. Our implementation with 4 virtual channels has an average network latency of 24 clock cycles and throughput of 62.5% of the network capacity for random traffic. For application specific traffic the latency is 6 clock cycles and throughput is 87% of the network capacity.

A fault-tolerant multi-transputer architecture

A new fault-tolerant multi-transputer architecture capable of tolerating failure of any one component in the system is described. In the proposed architecture the processing nodes are automatically reconfigured in the event of a fault and the computations continue from the stage where the fault occurred. The process of reconfiguration is transparent to the user, and the identity of the failed component is communicated to the user along with the results of computations. Parallel solution of a typical engineering problem involving solution of Laplace's equation by the boundary element method has been implemented. The performance of the architecture in the event of faults has been investigated.

Improving fault detection and reliability in FDDI networks

FDDI (Fibre Distributed Data Interface) is a 100 Mbit/s token ring network with two counter rotating optical rings. In this paper various possible faults (like lost token, link failures, etc.) are considered, and fault detection and the ring recovery process in case of a failure and the reliability mechanisms provided are studied. We suggest a new method to improve the fault detection and ring recovery process. The performance improvement in terms of station queue length and the average delay is compared with the performance of the existing fault detection and ring recovery process through simulation. We also suggest a modification for the physical configuration of the FDDI networks within the guidelines set by the standard to make the network more reliable. It is shown that, unlike the existing FDDI network, full connectivity is maintained among the stations even when multiple single link failures occur. A distributed algorithm is proposed for link reconfiguration of the modified FDDI network when many successive as well as simultaneous link failures occur. The performance of the modified FDDI network under link failures is studied through simulation and compared with that of the existing FDDI network.

A robust three phase power flow algorithm for radial distribution systems

An efficient load flow solution technique is required as a part of the distribution automation (DA) system for taking various control and operations decisions. This paper presents an efficient and robust three phase power flow algorithm for application to radial distribution networks. This method exploits the radial nature of the network and uses forward and backward propagation to calculate branch currents and node voltages. The proposed method has been tested to analyse several practical distribution networks of various voltage levels and also having high R/X ratio. The results for a practical distribution feeder are presented for illustration purposes. The application of the proposed method is also extended to find optimum location for reactive power compensation and network reconfiguration for planning and day-to-day operation of distribution networks.

USHA: unified software and hardware architecture for video decoding

Video decoders used in emerging applications need to be flexible to handle a large variety of video formats and deliver scalable performance to handle wide variations in workloads. In this paper we propose a unified software and hardware architecture for video decoding to achieve scalable performance with flexibility. The light weight processor tiles and the reconfigurable hardware tiles in our architecture enable software and hardware implementations to co-exist, while a programmable interconnect enables dynamic interconnection of the tiles. Our process network oriented compilation flow achieves realization agnostic application partitioning and enables seamless migration across uniprocessor, multi-processor, semi hardware and full hardware implementations of a video decoder. An application quality of service aware scheduler monitors and controls the operation of the entire system. We prove the concept through a prototype of the architecture on an off-the-shelf FPGA. The FPGA prototype shows a scaling in performance from QCIF to 1080p resolutions in four discrete steps. We also demonstrate that the reconfiguration time is short enough to allow migration from one configuration to the other without any frame loss.

HCN channels enhance spike phase coherence and regulate the phase of spikes and LFPs in the theta-frequency range

What are the implications for the existence of subthreshold ion channels, their localization profiles, and plasticity on local field potentials (LFPs)? Here, we assessed the role of hyperpolarization-activated cyclic-nucleotide-gated (HCN) channels in altering hippocampal theta-frequency LFPs and the associated spike phase. We presented spatiotemporally randomized, balanced theta-modulated excitatory and inhibitory inputs to somatically aligned, morphologically realistic pyramidal neuron models spread across a cylindrical neuropil. We computed LFPs from seven electrode sites and found that the insertion of an experimentally constrained HCN-conductance gradient into these neurons introduced a location- dependent lead in the LFP phase without significantly altering its amplitude. Further, neurons fired action potentials at a specific theta phase of the LFP, and the insertion of HCN channels introduced large lags in this spike phase and a striking enhancement in neuronal spike-phase coherence. Importantly, graded changes in either HCN conductance or its half-maximal activation voltage resulted in graded changes in LFP and spike phases. Our conclusions on the impact of HCN channels on LFPs and spike phase were invariant to changes in neuropil size, to morphological heterogeneity, to excitatory or inhibitory synaptic scaling, and to shifts in the onset phase of inhibitory inputs. Finally, we selectively abolished the inductive lead in the impedance phase introduced by HCN channels without altering neuronal excitability and found that this inductive phase lead contributed significantly to changes in LFP and spike phase. Our results uncover specific roles for HCN channels and their plasticity in phase-coding schemas and in the formation and dynamic reconfiguration of neuronal cell assemblies.